CMUX_0 Tile Documentation

Tile Bels

NameType
DCC_C0 DCC
DCC_C1 DCC
DCC_C2 DCC
DCC_C3 DCC

Config Bitmap

 
 
 
 
 
 
 
 
 
 
 
 
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

Routing Muxes

Mux driving N1:JHPRX0_CMUX_CORE_CMUX0

Source F12B0 F13B0 F14B0 F15B0 F16B0
G:JVPFS13_CMUX_CORE_CMUX0 0 0 1 0 1
G:JVPFS3_CMUX_CORE_CMUX0 0 0 1 1 0
G:JHPFW7_CMUX_CORE_CMUX0 0 0 1 1 1
G:JVPFS8_CMUX_CORE_CMUX0 0 1 0 0 1
G:JVPFN16_CMUX_CORE_CMUX0 0 1 0 1 1
G:JVPFN9_CMUX_CORE_CMUX0 0 1 1 0 1
G:JVPFS5_CMUX_CORE_CMUX0 0 1 1 1 0
N1:JDCS1_CMUX_CORE_CMUX0 0 1 1 1 1
G:JVPFS6_CMUX_CORE_CMUX0 1 0 0 0 1
G:JVPFN13_CMUX_CORE_CMUX0 1 0 0 1 1
G:JVPFN1_CMUX_CORE_CMUX0 1 0 1 0 1
G:JVPFS4_CMUX_CORE_CMUX0 1 0 1 1 0
N1:JJCLKLL_CMUX_CORE_CMUX0 1 0 1 1 1
G:JVPFS10_CMUX_CORE_CMUX0 1 1 0 0 1
G:JVPFS2_CMUX_CORE_CMUX0 1 1 0 1 0
G:JHPFW0_CMUX_CORE_CMUX0 1 1 0 1 1

Mux driving N1:JHPRX1_CMUX_CORE_CMUX0

Source F17B0 F18B0 F19B0 F20B0 F21B0
G:JHPFE4_CMUX_CORE_CMUX0 0 0 1 0 1
G:JVPFN2_CMUX_CORE_CMUX0 0 0 1 1 0
G:JHPFW7_CMUX_CORE_CMUX0 0 0 1 1 1
G:JVPFN14_CMUX_CORE_CMUX0 0 1 0 0 1
G:JHPFW3_CMUX_CORE_CMUX0 0 1 0 1 1
G:JHPFE9_CMUX_CORE_CMUX0 0 1 1 0 1
G:JVPFN9_CMUX_CORE_CMUX0 0 1 1 1 0
N1:JDCS1_CMUX_CORE_CMUX0 0 1 1 1 1
G:JVPFN11_CMUX_CORE_CMUX0 1 0 0 0 1
G:JHPFE10_CMUX_CORE_CMUX0 1 0 0 1 1
G:JHPFE6_CMUX_CORE_CMUX0 1 0 1 0 1
G:JVPFN7_CMUX_CORE_CMUX0 1 0 1 1 0
G:JHPFW8_CMUX_CORE_CMUX0 1 0 1 1 1
G:JVPFN15_CMUX_CORE_CMUX0 1 1 0 0 1
G:JVPFS14_CMUX_CORE_CMUX0 1 1 0 1 0
G:JHPFW5_CMUX_CORE_CMUX0 1 1 0 1 1

Mux driving N1:JHPRX2_CMUX_CORE_CMUX0

Source F22B0 F23B0 F24B0 F25B0 F26B0
G:JHPFE1_CMUX_CORE_CMUX0 0 0 1 0 1
G:JVPFS13_CMUX_CORE_CMUX0 0 0 1 1 0
G:JHPFE10_CMUX_CORE_CMUX0 0 0 1 1 1
G:JVPFN5_CMUX_CORE_CMUX0 0 1 0 0 1
G:JHPFE7_CMUX_CORE_CMUX0 0 1 0 1 1
G:JHPFE4_CMUX_CORE_CMUX0 0 1 1 0 1
G:JVPFN1_CMUX_CORE_CMUX0 0 1 1 1 0
N1:JJCLKLR_CMUX_CORE_CMUX0 0 1 1 1 1
G:JVPFN3_CMUX_CORE_CMUX0 1 0 0 0 1
G:JHPFE5_CMUX_CORE_CMUX0 1 0 0 1 1
G:JHPFE3_CMUX_CORE_CMUX0 1 0 1 0 1
G:JVPFN0_CMUX_CORE_CMUX0 1 0 1 1 0
N1:JJCLKUR_CMUX_CORE_CMUX0 1 0 1 1 1
G:JVPFN16_CMUX_CORE_CMUX0 1 1 0 0 1
G:JVPFS1_CMUX_CORE_CMUX0 1 1 0 1 0
G:JHPFE9_CMUX_CORE_CMUX0 1 1 0 1 1

Mux driving N1:JHPRX3_CMUX_CORE_CMUX0

Source F27B0 F28B0 F29B0 F30B0 F31B0
G:JHPFW1_CMUX_CORE_CMUX0 0 0 1 0 1
G:JVPFS9_CMUX_CORE_CMUX0 0 0 1 1 0
G:JHPFW10_CMUX_CORE_CMUX0 0 0 1 1 1
G:JHPFE5_CMUX_CORE_CMUX0 0 1 0 0 1
G:JHPFW7_CMUX_CORE_CMUX0 0 1 0 1 1
G:JHPFW5_CMUX_CORE_CMUX0 0 1 1 0 1
G:JVPFN10_CMUX_CORE_CMUX0 0 1 1 1 0
N1:JJCLKLL_CMUX_CORE_CMUX0 0 1 1 1 1
G:JHPFE3_CMUX_CORE_CMUX0 1 0 0 0 1
G:JHPFW6_CMUX_CORE_CMUX0 1 0 0 1 1
G:JHPFW3_CMUX_CORE_CMUX0 1 0 1 0 1
G:JVPFN0_CMUX_CORE_CMUX0 1 0 1 1 0
G:JHPFW11_CMUX_CORE_CMUX0 1 0 1 1 1
G:JHPFW0_CMUX_CORE_CMUX0 1 1 0 0 1
G:JVPFS3_CMUX_CORE_CMUX0 1 1 0 1 0
G:JHPFW9_CMUX_CORE_CMUX0 1 1 0 1 1

Mux driving N1:JHPRX4_CMUX_CORE_CMUX0

Source F32B0 F33B0 F34B0 F35B0 F36B0
G:JVPFN8_CMUX_CORE_CMUX0 0 0 1 0 1
G:JVPFS1_CMUX_CORE_CMUX0 0 0 1 1 0
G:JHPFE11_CMUX_CORE_CMUX0 0 0 1 1 1
G:JVPFN0_CMUX_CORE_CMUX0 0 1 0 0 1
G:JHPFE1_CMUX_CORE_CMUX0 0 1 0 1 1
G:JVPFN17_CMUX_CORE_CMUX0 0 1 1 0 1
G:JVPFS8_CMUX_CORE_CMUX0 0 1 1 1 0
N1:JJCLKLL_CMUX_CORE_CMUX0 0 1 1 1 1
G:JVPFS15_CMUX_CORE_CMUX0 1 0 0 0 1
G:JHPFE0_CMUX_CORE_CMUX0 1 0 0 1 1
G:JVPFN12_CMUX_CORE_CMUX0 1 0 1 0 1
G:JVPFS2_CMUX_CORE_CMUX0 1 0 1 1 0
G:JHPFW5_CMUX_CORE_CMUX0 1 0 1 1 1
G:JVPFN2_CMUX_CORE_CMUX0 1 1 0 0 1
G:JVPFS0_CMUX_CORE_CMUX0 1 1 0 1 0
G:JHPFE6_CMUX_CORE_CMUX0 1 1 0 1 1

Mux driving N1:JHPRX5_CMUX_CORE_CMUX0

Source F37B0 F38B0 F39B0 F40B0 F41B0
G:JVPFN7_CMUX_CORE_CMUX0 0 0 1 0 1
G:JVPFS2_CMUX_CORE_CMUX0 0 0 1 1 0
G:JHPFW9_CMUX_CORE_CMUX0 0 0 1 1 1
G:JVPFS10_CMUX_CORE_CMUX0 0 1 0 0 1
G:JHPFW1_CMUX_CORE_CMUX0 0 1 0 1 1
G:JHPFE4_CMUX_CORE_CMUX0 0 1 1 0 1
G:JVPFS4_CMUX_CORE_CMUX0 0 1 1 1 0
N1:JJCLKUL_CMUX_CORE_CMUX0 0 1 1 1 1
G:JVPFS7_CMUX_CORE_CMUX0 1 0 0 0 1
G:JHPFE8_CMUX_CORE_CMUX0 1 0 0 1 1
G:JHPFE1_CMUX_CORE_CMUX0 1 0 1 0 1
G:JVPFS3_CMUX_CORE_CMUX0 1 0 1 1 0
G:JHPFW10_CMUX_CORE_CMUX0 1 0 1 1 1
G:JVPFN5_CMUX_CORE_CMUX0 1 1 0 0 1
G:JVPFS0_CMUX_CORE_CMUX0 1 1 0 1 0
G:JHPFW8_CMUX_CORE_CMUX0 1 1 0 1 1

Mux driving N1:JHPRX6_CMUX_CORE_CMUX0

Source F42B0 F43B0 F44B0 F45B0 F46B0
G:JHPFE2_CMUX_CORE_CMUX0 0 0 1 0 1
G:JVPFS11_CMUX_CORE_CMUX0 0 0 1 1 0
G:JHPFW8_CMUX_CORE_CMUX0 0 0 1 1 1
G:JVPFN11_CMUX_CORE_CMUX0 0 1 0 0 1
G:JHPFW4_CMUX_CORE_CMUX0 0 1 0 1 1
G:JHPFE7_CMUX_CORE_CMUX0 0 1 1 0 1
G:JVPFS13_CMUX_CORE_CMUX0 0 1 1 1 0
G:JHPFW11_CMUX_CORE_CMUX0 0 1 1 1 1
G:JVPFS15_CMUX_CORE_CMUX0 1 0 0 0 1
G:JHPFE8_CMUX_CORE_CMUX0 1 0 0 1 1
G:JHPFE3_CMUX_CORE_CMUX0 1 0 1 0 1
G:JVPFS12_CMUX_CORE_CMUX0 1 0 1 1 0
G:JHPFW10_CMUX_CORE_CMUX0 1 0 1 1 1
G:JVPFN17_CMUX_CORE_CMUX0 1 1 0 0 1
G:JVPFS2_CMUX_CORE_CMUX0 1 1 0 1 0
G:JHPFW7_CMUX_CORE_CMUX0 1 1 0 1 1

Mux driving N1:JHPRX7_CMUX_CORE_CMUX0

Source F47B0 F48B0 F49B0 F50B0 F51B0
G:JVPFN13_CMUX_CORE_CMUX0 0 0 1 0 1
G:JVPFS7_CMUX_CORE_CMUX0 0 0 1 1 0
G:JHPFW1_CMUX_CORE_CMUX0 0 0 1 1 1
G:JVPFN6_CMUX_CORE_CMUX0 0 1 0 0 1
G:JHPFE4_CMUX_CORE_CMUX0 0 1 0 1 1
G:JVPFN16_CMUX_CORE_CMUX0 0 1 1 0 1
G:JVPFS14_CMUX_CORE_CMUX0 0 1 1 1 0
N1:JDCS0_CMUX_CORE_CMUX0 0 1 1 1 1
G:JVPFS15_CMUX_CORE_CMUX0 1 0 0 0 1
G:JHPFE0_CMUX_CORE_CMUX0 1 0 0 1 1
G:JVPFN15_CMUX_CORE_CMUX0 1 0 1 0 1
G:JVPFS12_CMUX_CORE_CMUX0 1 0 1 1 0
N1:JJCLKLL_CMUX_CORE_CMUX0 1 0 1 1 1
G:JVPFN11_CMUX_CORE_CMUX0 1 1 0 0 1
G:JVPFS5_CMUX_CORE_CMUX0 1 1 0 1 0
G:JHPFE5_CMUX_CORE_CMUX0 1 1 0 1 1

Fixed Connections

SourceSink
N1:JCIBMUXOUTA7→ N1:JCE_DCC_DCC0
N1:JCIBMUXOUTA0→ N1:JCE_DCC_DCC1
N1E1:JCIBMUXOUTD5→ N1:JCE_DCC_DCC2
N1E1:JCIBMUXOUTD6→ N1:JCE_DCC_DCC3
N1:JCLKOUT_PCLKDIV_PCLKDIV0→ N1:JCLK0_DCS_DCSIP0
N1:JCLKOUT_PCLKDIV_PCLKDIV1→ N1:JCLK0_DCS_DCSIP1
N1:JDCSMUXOUT_DCSMUX_CORE_DCSMUX1→ N1:JCLK1_DCS_DCSIP0
N1:JDCSMUXOUT_DCSMUX_CORE_DCSMUX3→ N1:JCLK1_DCS_DCSIP1
N1:JDCSMUXOUT_DCSMUX_CORE_DCSMUX0→ N1:JCLKIN_PCLKDIV_PCLKDIV0
N1:JDCSMUXOUT_DCSMUX_CORE_DCSMUX2→ N1:JCLKIN_PCLKDIV_PCLKDIV1
N1:JCIBMUXOUTD6→ N1:JCLKI_DCC_DCC0
N1:JCIBMUXOUTD7→ N1:JCLKI_DCC_DCC1
N1E1:JCIBMUXOUTD3→ N1:JCLKI_DCC_DCC2
N1E1:JCIBMUXOUTD4→ N1:JCLKI_DCC_DCC3
N1:JCLKIN_PCLKDIV_PCLKDIV0→ N1:JCLKOUT_PCLKDIV_PCLKDIV0
N1:JCLKIN_PCLKDIV_PCLKDIV1→ N1:JCLKOUT_PCLKDIV_PCLKDIV1
N1:JCLKI_DCC_DCC0→ N1:JCLKO_DCC_DCC0
N1:JCLKI_DCC_DCC1→ N1:JCLKO_DCC_DCC1
N1:JCLKI_DCC_DCC2→ N1:JCLKO_DCC_DCC2
N1:JCLKI_DCC_DCC3→ N1:JCLKO_DCC_DCC3
N1E1:JCLK1→ N1:JCLK_GSR_CORE_GSR_CENTER
N1:JDCSOUT_DCS_DCSIP0→ N1:JDCS0_CMUX_CORE_CMUX0
N1:JDCSOUT_DCS_DCSIP0→ N1:JDCS0_CMUX_CORE_CMUX1
N1:JDCSOUT_DCS_DCSIP0→ N1:JDCS0_CMUX_CORE_CMUX2
N1:JDCSOUT_DCS_DCSIP0→ N1:JDCS0_CMUX_CORE_CMUX3
N1:JDCSOUT_DCS_DCSIP1→ N1:JDCS1_CMUX_CORE_CMUX0
N1:JDCSOUT_DCS_DCSIP1→ N1:JDCS1_CMUX_CORE_CMUX1
N1:JDCSOUT_DCS_DCSIP1→ N1:JDCS1_CMUX_CORE_CMUX2
N1:JDCSOUT_DCS_DCSIP1→ N1:JDCS1_CMUX_CORE_CMUX3
N1:JCLK0_DCS_DCSIP0→ N1:JDCSOUT_DCS_DCSIP0
N1:JCLK1_DCS_DCSIP0→ N1:JDCSOUT_DCS_DCSIP0
N1:JCLK0_DCS_DCSIP1→ N1:JDCSOUT_DCS_DCSIP1
N1:JCLK1_DCS_DCSIP1→ N1:JDCSOUT_DCS_DCSIP1
N1E1:JCIBMUXOUTB3→ N1:JGSR_N_GSR_CORE_GSR_CENTER
N1:JCLKO_DCC_DCC2→ N1:JJCLKLL_CMUX_CORE_CMUX0
N1:JCLKO_DCC_DCC2→ N1:JJCLKLL_CMUX_CORE_CMUX1
N1:JCLKO_DCC_DCC2→ N1:JJCLKLL_CMUX_CORE_CMUX2
N1:JCLKO_DCC_DCC2→ N1:JJCLKLL_CMUX_CORE_CMUX3
N1:JCLKO_DCC_DCC2→ N1:JJCLKLL_DCSMUX_CORE_DCSMUX0
N1:JCLKO_DCC_DCC2→ N1:JJCLKLL_DCSMUX_CORE_DCSMUX1
N1:JCLKO_DCC_DCC2→ N1:JJCLKLL_DCSMUX_CORE_DCSMUX2
N1:JCLKO_DCC_DCC2→ N1:JJCLKLL_DCSMUX_CORE_DCSMUX3
N1:JCLKO_DCC_DCC3→ N1:JJCLKLR_CMUX_CORE_CMUX0
N1:JCLKO_DCC_DCC3→ N1:JJCLKLR_CMUX_CORE_CMUX1
N1:JCLKO_DCC_DCC3→ N1:JJCLKLR_CMUX_CORE_CMUX2
N1:JCLKO_DCC_DCC3→ N1:JJCLKLR_CMUX_CORE_CMUX3
N1:JCLKO_DCC_DCC3→ N1:JJCLKLR_DCSMUX_CORE_DCSMUX0
N1:JCLKO_DCC_DCC3→ N1:JJCLKLR_DCSMUX_CORE_DCSMUX1
N1:JCLKO_DCC_DCC3→ N1:JJCLKLR_DCSMUX_CORE_DCSMUX2
N1:JCLKO_DCC_DCC3→ N1:JJCLKLR_DCSMUX_CORE_DCSMUX3
N1:JCLKO_DCC_DCC0→ N1:JJCLKUL_CMUX_CORE_CMUX0
N1:JCLKO_DCC_DCC0→ N1:JJCLKUL_CMUX_CORE_CMUX1
N1:JCLKO_DCC_DCC0→ N1:JJCLKUL_CMUX_CORE_CMUX2
N1:JCLKO_DCC_DCC0→ N1:JJCLKUL_CMUX_CORE_CMUX3
N1:JCLKO_DCC_DCC0→ N1:JJCLKUL_DCSMUX_CORE_DCSMUX0
N1:JCLKO_DCC_DCC0→ N1:JJCLKUL_DCSMUX_CORE_DCSMUX1
N1:JCLKO_DCC_DCC0→ N1:JJCLKUL_DCSMUX_CORE_DCSMUX2
N1:JCLKO_DCC_DCC0→ N1:JJCLKUL_DCSMUX_CORE_DCSMUX3
N1:JCLKO_DCC_DCC1→ N1:JJCLKUR_CMUX_CORE_CMUX0
N1:JCLKO_DCC_DCC1→ N1:JJCLKUR_CMUX_CORE_CMUX1
N1:JCLKO_DCC_DCC1→ N1:JJCLKUR_CMUX_CORE_CMUX2
N1:JCLKO_DCC_DCC1→ N1:JJCLKUR_CMUX_CORE_CMUX3
N1:JCLKO_DCC_DCC1→ N1:JJCLKUR_DCSMUX_CORE_DCSMUX0
N1:JCLKO_DCC_DCC1→ N1:JJCLKUR_DCSMUX_CORE_DCSMUX1
N1:JCLKO_DCC_DCC1→ N1:JJCLKUR_DCSMUX_CORE_DCSMUX2
N1:JCLKO_DCC_DCC1→ N1:JJCLKUR_DCSMUX_CORE_DCSMUX3
N1:JCIBMUXOUTA1→ N1:JLSRPDIV_PCLKDIV_PCLKDIV0
S8:JLSR0→ N1:JLSRPDIV_PCLKDIV_PCLKDIV1
N1E1:JCIBMUXOUTD0→ N1:JPCLKDIVTESTINP0_PCLKDIV_PCLKDIV0
S8E1:JCIBMUXOUTD0→ N1:JPCLKDIVTESTINP0_PCLKDIV_PCLKDIV1
N1E1:JCIBMUXOUTD1→ N1:JPCLKDIVTESTINP1_PCLKDIV_PCLKDIV0
S8E1:JCIBMUXOUTD1→ N1:JPCLKDIVTESTINP1_PCLKDIV_PCLKDIV1
N1E1:JCIBMUXOUTD2→ N1:JPCLKDIVTESTINP2_PCLKDIV_PCLKDIV0
S8E1:JCIBMUXOUTD2→ N1:JPCLKDIVTESTINP2_PCLKDIV_PCLKDIV1
N1E1:JCIBMUXOUTC7→ N1:JSELFORCE_DCS_DCSIP0
S8E1:JCIBMUXOUTC7→ N1:JSELFORCE_DCS_DCSIP1
N1E1:JCIBMUXOUTC6→ N1:JSEL_DCS_DCSIP0
S8E1:JCIBMUXOUTC6→ N1:JSEL_DCS_DCSIP1
N1E1:JCIBMUXOUTA0→ N1:JTESTINP0_CMUX_CORE_CMUX0
N1E1:JCIBMUXOUTA5→ N1:JTESTINP0_CMUX_CORE_CMUX1
S8E1:JCIBMUXOUTA0→ N1:JTESTINP0_CMUX_CORE_CMUX2
S8E1:JCIBMUXOUTA5→ N1:JTESTINP0_CMUX_CORE_CMUX3
N1:JCIBMUXOUTB0→ N1:JTESTINP0_DCSMUX_CORE_DCSMUX0
N1:JCIBMUXOUTC1→ N1:JTESTINP0_DCSMUX_CORE_DCSMUX1
S8:JCIBMUXOUTB0→ N1:JTESTINP0_DCSMUX_CORE_DCSMUX2
S8:JCIBMUXOUTC1→ N1:JTESTINP0_DCSMUX_CORE_DCSMUX3
N1E1:JCIBMUXOUTA1→ N1:JTESTINP1_CMUX_CORE_CMUX0
N1E1:JCIBMUXOUTA6→ N1:JTESTINP1_CMUX_CORE_CMUX1
S8E1:JCIBMUXOUTA1→ N1:JTESTINP1_CMUX_CORE_CMUX2
S8E1:JCIBMUXOUTA6→ N1:JTESTINP1_CMUX_CORE_CMUX3
N1:JCIBMUXOUTB1→ N1:JTESTINP1_DCSMUX_CORE_DCSMUX0
N1:JCIBMUXOUTC3→ N1:JTESTINP1_DCSMUX_CORE_DCSMUX1
S8:JCIBMUXOUTB1→ N1:JTESTINP1_DCSMUX_CORE_DCSMUX2
S8:JCIBMUXOUTC3→ N1:JTESTINP1_DCSMUX_CORE_DCSMUX3
N1E1:JCIBMUXOUTA2→ N1:JTESTINP2_CMUX_CORE_CMUX0
N1E1:JCIBMUXOUTA7→ N1:JTESTINP2_CMUX_CORE_CMUX1
S8E1:JCIBMUXOUTA2→ N1:JTESTINP2_CMUX_CORE_CMUX2
S8E1:JCIBMUXOUTA7→ N1:JTESTINP2_CMUX_CORE_CMUX3
N1:JCIBMUXOUTB2→ N1:JTESTINP2_DCSMUX_CORE_DCSMUX0
N1:JCIBMUXOUTC5→ N1:JTESTINP2_DCSMUX_CORE_DCSMUX1
S8:JCIBMUXOUTB2→ N1:JTESTINP2_DCSMUX_CORE_DCSMUX2
S8:JCIBMUXOUTC5→ N1:JTESTINP2_DCSMUX_CORE_DCSMUX3
N1E1:JCIBMUXOUTA3→ N1:JTESTINP3_CMUX_CORE_CMUX0
N1E1:JCIBMUXOUTC0→ N1:JTESTINP3_CMUX_CORE_CMUX1
S8E1:JCIBMUXOUTA3→ N1:JTESTINP3_CMUX_CORE_CMUX2
S8E1:JCIBMUXOUTC0→ N1:JTESTINP3_CMUX_CORE_CMUX3
N1:JCIBMUXOUTB3→ N1:JTESTINP3_DCSMUX_CORE_DCSMUX0
N1:JCIBMUXOUTC7→ N1:JTESTINP3_DCSMUX_CORE_DCSMUX1
S8:JCIBMUXOUTB3→ N1:JTESTINP3_DCSMUX_CORE_DCSMUX2
S8:JCIBMUXOUTC7→ N1:JTESTINP3_DCSMUX_CORE_DCSMUX3
N1E1:JCIBMUXOUTA4→ N1:JTESTINP4_CMUX_CORE_CMUX0
N1E1:JCIBMUXOUTC1→ N1:JTESTINP4_CMUX_CORE_CMUX1
S8E1:JCIBMUXOUTA4→ N1:JTESTINP4_CMUX_CORE_CMUX2
S8E1:JCIBMUXOUTC1→ N1:JTESTINP4_CMUX_CORE_CMUX3
N1:JCIBMUXOUTB4→ N1:JTESTINP4_DCSMUX_CORE_DCSMUX0
N1:JCIBMUXOUTD0→ N1:JTESTINP4_DCSMUX_CORE_DCSMUX1
S8:JCIBMUXOUTB4→ N1:JTESTINP4_DCSMUX_CORE_DCSMUX2
S8:JCIBMUXOUTD0→ N1:JTESTINP4_DCSMUX_CORE_DCSMUX3
N1:JCIBMUXOUTB5→ N1:JTESTINP5_DCSMUX_CORE_DCSMUX0
N1:JCIBMUXOUTD2→ N1:JTESTINP5_DCSMUX_CORE_DCSMUX1
S8:JCIBMUXOUTB5→ N1:JTESTINP5_DCSMUX_CORE_DCSMUX2
S8:JCIBMUXOUTD2→ N1:JTESTINP5_DCSMUX_CORE_DCSMUX3
N1:JCIBMUXOUTB6→ N1:JTESTINP6_DCSMUX_CORE_DCSMUX0
N1:JCIBMUXOUTD4→ N1:JTESTINP6_DCSMUX_CORE_DCSMUX1
S8:JCIBMUXOUTB6→ N1:JTESTINP6_DCSMUX_CORE_DCSMUX2
S8:JCIBMUXOUTD4→ N1:JTESTINP6_DCSMUX_CORE_DCSMUX3