CMUX_0/DCS0 (DCS) Bel Documentation

Bel Pins

PinWire
CLK0 N1:JCLK0_DCS_DCSIPClock input port 0 (default)
CLK1 N1:JCLK1_DCS_DCSIPClock input port 1
SEL N1:JSEL_DCS_DCSIPInput clock select
SELFORCE N1:JSELFORCE_DCS_DCSIPSelects glitchless (0) or non-glitchless (1) behavior
DCSOUT N1:JDCSOUT_DCS_DCSIPClock output port