The format of the bitstream has many similarities to ECP5 and previous Lattice devices. It is still a command-based format with many similar commands, albeit with changes for some of the new features.
The first four bytes of the bitstream are 0x4C 0x53 0x43 0x43 (LSCC, i.e. Lattice SemiConductor Corporation). (TODO: test - this may be needed for SPI flash boot to work.)
This the follows an option comment section, which is bounded by 0xFF 0x00 and 0x00 0xFF. It contains several null-terminated strings used by tools like Radiant Programmer to determine the device, package, build date/time etc. It is not parsed by the chip.
The four bytes marking the start of an actual bitstream are 0xFF 0xFF 0xBD 0xB3, the same as the ECP5.
All commands (except the 0xFF dummy command) are followed by three "parameter" bytes and then zero or more bytes of payload. All multi-byte integers are big endian.
0x3B): resets the internal CRC16 counter0xE2): after th 3 param bytes; followed by the 32-bit device IDCODE. Config ends if IDCODE does not match0x22): sets the value of control register 0, which contains various settings such as config clock frequency and multiboot mode0x46): sets the frame address counter to 00xB4): sets the frame address counter to the 32-bit payload0x82): programs configuration frames at incrementing addresses. First param byte contains general settings and next two contain 16-bit frame count. See Config Frames section for more info0xC2): sets the usercode to the 32-bit payload0xF6): sets the IP/RAM bus address to the 32-bit payload0x72): writes to the IP/RAM bus at incrementing addresses. First param byte contains general settings and next two contain 16-bit word count0x5E): ends configuration and starts FPGA fabric running0x56): third param byte configures internal power switches (detail unknown)Config frames are written in three chunks (numbers for LIFCL):
It is believed this ordering is for the "early IO release" feature.
The final 14 bits of each config frame are used for an error correcting code ("parity"). This uses the typical CRC algorithm with polynomial 0x202D.
The error correcting code does not include LUT RAM initialisation bits, these are masked with zeroes, because they can change at runtime.
Following each frame is the standard packet CRC16, which uses the common 0x8005 polynomial.
IP and RAM configuration and initialisation is not done using general configuration frames but using a special bus, which for IP mirrors the LMMI bus exposed to fabric.
The first byte of the 32-bit bus address is used to determine the destination type, and the word size for LSC_BUS_WRITE: