TMID_1 Tile Documentation

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Routing Muxes

Mux driving G:JVPFS10_TMID_CORE_TMIDMUX

Source F30B0 F31B0 F32B0 F33B0
G:JPCIECLKRX0_TMID_CORE_TMIDMUX 0 1 1 1
G:JPCLKCIBT2_TMID_CORE_TMIDMUX 1 0 0 1
G:JPCLKT00_TMID_CORE_TMIDMUX 1 0 1 1
G:JCLKHSBYTE1_TMID_CORE_TMIDMUX 1 1 0 0
G:JMIPIDPHY0RX_TMID_CORE_TMIDMUX 1 1 1 0
G:JULCLKOS3_TMID_CORE_TMIDMUX 1 1 1 1

Mux driving G:JVPFS11_TMID_CORE_TMIDMUX

Source F35B0 F36B0 F37B0 F38B0
G:JPCIEUSRCLK0_TMID_CORE_TMIDMUX 0 1 1 0
G:JCLKHSBYTE0_TMID_CORE_TMIDMUX 0 1 1 1
G:JPCLKCIBT3_TMID_CORE_TMIDMUX 1 0 0 1
G:JPCLKT01_TMID_CORE_TMIDMUX 1 0 1 1
G:JULCLKOS2_TMID_CORE_TMIDMUX 1 1 0 1
G:JOSCLF_TMID_CORE_TMIDMUX 1 1 1 1

Mux driving G:JVPFS12_TMID_CORE_TMIDMUX

Source F40B0 F41B0 F42B0 F43B0
G:JPCLKCIBT1_TMID_CORE_TMIDMUX 0 1 0 0
G:JPCLKCIBT4_TMID_CORE_TMIDMUX 1 0 1 1
G:JPCIECLKRX0_TMID_CORE_TMIDMUX 1 1 0 0
G:JULCLKOP_TMID_CORE_TMIDMUX 1 1 0 1
G:JJTCLK_TMID_CORE_TMIDMUX 1 1 1 1

Mux driving G:JVPFS13_TMID_CORE_TMIDMUX

Source F45B0 F46B0 F47B0 F48B0
G:JPCLKT00_TMID_CORE_TMIDMUX 0 1 0 0
G:JPCIELINKCLK0_TMID_CORE_TMIDMUX 0 1 1 0
G:JPCLKCIBT1_TMID_CORE_TMIDMUX 1 0 1 1
G:JCLKHSBYTE1_TMID_CORE_TMIDMUX 1 1 0 0
G:JULCLKOS_TMID_CORE_TMIDMUX 1 1 0 1
G:JMIPIDPHY0TX_TMID_CORE_TMIDMUX 1 1 1 0
G:JOSCHF_TMID_CORE_TMIDMUX 1 1 1 1

Mux driving G:JVPFS14_TMID_CORE_TMIDMUX

Source F50B0 F51B0 F52B0 F53B0
G:JPCIEUSRCLK0_TMID_CORE_TMIDMUX 0 1 1 0
G:JPCIECLKTX0_TMID_CORE_TMIDMUX 0 1 1 1
G:JPCLKCIBT5_TMID_CORE_TMIDMUX 1 0 0 1
G:JPCLKCIBT2_TMID_CORE_TMIDMUX 1 0 1 1
G:JMIPIDPHY1RX_TMID_CORE_TMIDMUX 1 1 0 0
G:JULCLKOS_TMID_CORE_TMIDMUX 1 1 0 1
G:JOSCLF_TMID_CORE_TMIDMUX 1 1 1 1

Mux driving G:JVPFS15_TMID_CORE_TMIDMUX

Source F55B0 F56B0 F57B0 F58B0
G:JPCLKCIBT0_TMID_CORE_TMIDMUX 0 1 0 0
G:JPCLKCIBT4_TMID_CORE_TMIDMUX 1 0 1 1
G:JMIPIDPHY1TX_TMID_CORE_TMIDMUX 1 1 0 0
G:JULCLKOS3_TMID_CORE_TMIDMUX 1 1 0 1
G:JMIPIDPHY0RX_TMID_CORE_TMIDMUX 1 1 1 0
G:JJTCLK_TMID_CORE_TMIDMUX 1 1 1 1

Mux driving G:JVPFS8_TMID_CORE_TMIDMUX

Source F20B0 F21B0 F22B0 F23B0
G:JPCIEUSRCLK0_TMID_CORE_TMIDMUX 0 1 1 0
G:JMIPIDPHY1RX_TMID_CORE_TMIDMUX 0 1 1 1
G:JPCLKCIBT0_TMID_CORE_TMIDMUX 1 0 0 1
G:JPCLKT00_TMID_CORE_TMIDMUX 1 0 1 1
G:JCLKHSBYTE0_TMID_CORE_TMIDMUX 1 1 0 0
G:JULCLKOP_TMID_CORE_TMIDMUX 1 1 1 1

Mux driving G:JVPFS9_TMID_CORE_TMIDMUX

Source F25B0 F26B0 F27B0 F28B0
G:JPCIECLKTX0_TMID_CORE_TMIDMUX 0 1 0 1
G:JPCIELINKCLK0_TMID_CORE_TMIDMUX 0 1 1 0
G:JMIPIDPHY1TX_TMID_CORE_TMIDMUX 0 1 1 1
G:JPCLKCIBT4_TMID_CORE_TMIDMUX 1 0 0 1
G:JPCLKCIBT1_TMID_CORE_TMIDMUX 1 0 1 1
G:JMIPIDPHY0TX_TMID_CORE_TMIDMUX 1 1 0 0
G:JULCLKOS2_TMID_CORE_TMIDMUX 1 1 0 1
G:JOSCHF_TMID_CORE_TMIDMUX 1 1 1 1

Configuration Enums

Configuration enum DCC_T10.DCCEN

DCC bypassed (0) or used as gate (1)

Value F12B0
0 -
1 1

Configuration enum DCC_T11.DCCEN

DCC bypassed (0) or used as gate (1)

Value F13B0
0 -
1 1

Configuration enum DCC_T12.DCCEN

DCC bypassed (0) or used as gate (1)

Value F14B0
0 -
1 1

Configuration enum DCC_T13.DCCEN

DCC bypassed (0) or used as gate (1)

Value F15B0
0 -
1 1

Configuration enum DCC_T14.DCCEN

DCC bypassed (0) or used as gate (1)

Value F16B0
0 -
1 1

Configuration enum DCC_T15.DCCEN

DCC bypassed (0) or used as gate (1)

Value F17B0
0 -
1 1

Configuration enum DCC_T8.DCCEN

DCC bypassed (0) or used as gate (1)

Value F10B0
0 -
1 1

Configuration enum DCC_T9.DCCEN

DCC bypassed (0) or used as gate (1)

Value F11B0
0 -
1 1