TMID_0 Tile Documentation

Tile Bels

NameType
DCC_T0 DCC
DCC_T1 DCC
DCC_T2 DCC
DCC_T3 DCC
DCC_T4 DCC
DCC_T5 DCC
DCC_T6 DCC
DCC_T7 DCC
DCC_T8 DCC
DCC_T9 DCC
DCC_T10 DCC
DCC_T11 DCC
DCC_T12 DCC
DCC_T13 DCC
DCC_T14 DCC
DCC_T15 DCC

Config Bitmap

 
 
 
 
 
 
 
 
 
 
D
D
D
D
D
D
D
D
 
 
T
T
T
T
 
T
T
T
T
 
T
T
T
T
 
T
T
T
T
 
T
T
T
T
 
T
T
T
T
 
T
T
T
T
 
T
T
T
T
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

Routing Muxes

Mux driving G:JVPFS0_TMID_CORE_TMIDMUX

Source F20B0 F21B0 F22B0 F23B0
G:JPCIECLKRX0_TMID_CORE_TMIDMUX 0 1 1 1
G:JPCLKCIBT3_TMID_CORE_TMIDMUX 1 0 0 1
G:JPCLKT01_TMID_CORE_TMIDMUX 1 0 1 1
G:JULCLKOP_TMID_CORE_TMIDMUX 1 1 0 1
G:JJTCLK_TMID_CORE_TMIDMUX 1 1 1 1

Mux driving G:JVPFS1_TMID_CORE_TMIDMUX

Source F25B0 F26B0 F27B0 F28B0
G:JPCIELINKCLK0_TMID_CORE_TMIDMUX 0 1 1 0
G:JPCLKCIBT5_TMID_CORE_TMIDMUX 1 0 0 1
G:JPCLKCIBT1_TMID_CORE_TMIDMUX 1 0 1 1
G:JCLKHSBYTE1_TMID_CORE_TMIDMUX 1 1 0 0
G:JULCLKOS3_TMID_CORE_TMIDMUX 1 1 0 1
G:JMIPIDPHY0TX_TMID_CORE_TMIDMUX 1 1 1 0
G:JOSCHF_TMID_CORE_TMIDMUX 1 1 1 1

Mux driving G:JVPFS2_TMID_CORE_TMIDMUX

Source F30B0 F31B0 F32B0 F33B0
G:JPCIECLKTX0_TMID_CORE_TMIDMUX 0 1 0 1
G:JMIPIDPHY1TX_TMID_CORE_TMIDMUX 0 1 1 1
G:JPCLKCIBT2_TMID_CORE_TMIDMUX 1 0 0 1
G:JPCLKT01_TMID_CORE_TMIDMUX 1 0 1 1
G:JCLKHSBYTE0_TMID_CORE_TMIDMUX 1 1 0 0
G:JULCLKOS2_TMID_CORE_TMIDMUX 1 1 0 1
G:JOSCLF_TMID_CORE_TMIDMUX 1 1 1 1

Mux driving G:JVPFS3_TMID_CORE_TMIDMUX

Source F35B0 F36B0 F37B0 F38B0
G:JMIPIDPHY1RX_TMID_CORE_TMIDMUX 0 1 1 1
G:JPCLKCIBT4_TMID_CORE_TMIDMUX 1 0 0 1
G:JMIPIDPHY0RX_TMID_CORE_TMIDMUX 1 1 0 0
G:JULCLKOP_TMID_CORE_TMIDMUX 1 1 0 1
G:JJTCLK_TMID_CORE_TMIDMUX 1 1 1 1

Mux driving G:JVPFS4_TMID_CORE_TMIDMUX

Source F40B0 F41B0 F42B0 F43B0
G:JPCIELINKCLK0_TMID_CORE_TMIDMUX 0 1 1 0
G:JPCIECLKTX0_TMID_CORE_TMIDMUX 0 1 1 1
G:JPCLKCIBT5_TMID_CORE_TMIDMUX 1 0 0 1
G:JPCLKCIBT3_TMID_CORE_TMIDMUX 1 0 1 1
G:JMIPIDPHY1RX_TMID_CORE_TMIDMUX 1 1 0 0
G:JMIPIDPHY0RX_TMID_CORE_TMIDMUX 1 1 1 0
G:JULCLKOS_TMID_CORE_TMIDMUX 1 1 1 1

Mux driving G:JVPFS5_TMID_CORE_TMIDMUX

Source F45B0 F46B0 F47B0 F48B0
G:JPCIEUSRCLK0_TMID_CORE_TMIDMUX 0 1 1 0
G:JMIPIDPHY1TX_TMID_CORE_TMIDMUX 0 1 1 1
G:JPCLKCIBT3_TMID_CORE_TMIDMUX 1 0 0 1
G:JPCLKCIBT0_TMID_CORE_TMIDMUX 1 0 1 1
G:JULCLKOS2_TMID_CORE_TMIDMUX 1 1 0 1
G:JOSCLF_TMID_CORE_TMIDMUX 1 1 1 1

Mux driving G:JVPFS6_TMID_CORE_TMIDMUX

Source F50B0 F51B0 F52B0 F53B0
G:JPCLKT00_TMID_CORE_TMIDMUX 0 1 0 0
G:JPCLKCIBT5_TMID_CORE_TMIDMUX 1 0 0 1
G:JPCLKCIBT0_TMID_CORE_TMIDMUX 1 0 1 1
G:JCLKHSBYTE1_TMID_CORE_TMIDMUX 1 1 0 0
G:JULCLKOS3_TMID_CORE_TMIDMUX 1 1 0 1
G:JMIPIDPHY0TX_TMID_CORE_TMIDMUX 1 1 1 0
G:JOSCHF_TMID_CORE_TMIDMUX 1 1 1 1

Mux driving G:JVPFS7_TMID_CORE_TMIDMUX

Source F55B0 F56B0 F57B0 F58B0
G:JPCLKT01_TMID_CORE_TMIDMUX 0 1 0 0
G:JPCLKCIBT2_TMID_CORE_TMIDMUX 1 0 1 1
G:JPCIECLKRX0_TMID_CORE_TMIDMUX 1 1 0 0
G:JCLKHSBYTE0_TMID_CORE_TMIDMUX 1 1 1 0
G:JULCLKOS_TMID_CORE_TMIDMUX 1 1 1 1

Configuration Enums

Configuration enum DCC_T0.DCCEN

DCC bypassed (0) or used as gate (1)

Value F10B0
0 -
1 1

Configuration enum DCC_T1.DCCEN

DCC bypassed (0) or used as gate (1)

Value F11B0
0 -
1 1

Configuration enum DCC_T2.DCCEN

DCC bypassed (0) or used as gate (1)

Value F12B0
0 -
1 1

Configuration enum DCC_T3.DCCEN

DCC bypassed (0) or used as gate (1)

Value F13B0
0 -
1 1

Configuration enum DCC_T4.DCCEN

DCC bypassed (0) or used as gate (1)

Value F14B0
0 -
1 1

Configuration enum DCC_T5.DCCEN

DCC bypassed (0) or used as gate (1)

Value F15B0
0 -
1 1

Configuration enum DCC_T6.DCCEN

DCC bypassed (0) or used as gate (1)

Value F16B0
0 -
1 1

Configuration enum DCC_T7.DCCEN

DCC bypassed (0) or used as gate (1)

Value F17B0
0 -
1 1

Fixed Connections

SourceSink
S1W2:JCIBMUXOUTD7→ G:JPCLKCIBT0_TMID_CORE_TMIDMUX
S1W1:JCIBMUXOUTD7→ G:JPCLKCIBT1_TMID_CORE_TMIDMUX
S1:JCIBMUXOUTD7→ G:JPCLKCIBT2_TMID_CORE_TMIDMUX
S1E1:JCIBMUXOUTD7→ G:JPCLKCIBT3_TMID_CORE_TMIDMUX
S1E2:JCIBMUXOUTD7→ G:JPCLKCIBT4_TMID_CORE_TMIDMUX
S1E3:JCIBMUXOUTD7→ G:JPCLKCIBT5_TMID_CORE_TMIDMUX
E27:JINCK_SIOLOGIC_CORE_IBASE_PIC_A→ G:JPCLKT00_TMID_CORE_TMIDMUX
E27:JPADDI_SEIO33_CORE_IOA→ G:JPCLKT00_TMID_CORE_TMIDMUX
E22:JINCK_SIOLOGIC_CORE_IBASE_PIC_A→ G:JPCLKT00_TMID_CORE_TMIDMUX
E22:JPADDI_SEIO33_CORE_IOA→ G:JPCLKT00_TMID_CORE_TMIDMUX
E29:JINCK_SIOLOGIC_CORE_IBASE_PIC_A→ G:JPCLKT01_TMID_CORE_TMIDMUX
E29:JPADDI_SEIO33_CORE_IOA→ G:JPCLKT01_TMID_CORE_TMIDMUX
E24:JINCK_SIOLOGIC_CORE_IBASE_PIC_A→ G:JPCLKT01_TMID_CORE_TMIDMUX
E24:JPADDI_SEIO33_CORE_IOA→ G:JPCLKT01_TMID_CORE_TMIDMUX
S1:JCIBMUXOUTA4→ G:JTESTINP0_TMID_CORE_TMIDMUX
S1:JCIBMUXOUTA5→ G:JTESTINP1_TMID_CORE_TMIDMUX
S1:JCIBMUXOUTA6→ G:JTESTINP2_TMID_CORE_TMIDMUX
S1:JCIBMUXOUTA7→ G:JTESTINP3_TMID_CORE_TMIDMUX
JCLKO_DCC_DCC0→ G:JVPFS0_CMUX_CORE_CMUX0
JCLKO_DCC_DCC0→ G:JVPFS0_CMUX_CORE_CMUX1
JCLKO_DCC_DCC0→ G:JVPFS0_DCSMUX_CORE_DCSMUX0
JCLKO_DCC_DCC0→ G:JVPFS0_DCSMUX_CORE_DCSMUX1
JCLKO_DCC_DCC10→ G:JVPFS10_CMUX_CORE_CMUX0
JCLKO_DCC_DCC10→ G:JVPFS10_CMUX_CORE_CMUX1
JCLKO_DCC_DCC10→ G:JVPFS10_DCSMUX_CORE_DCSMUX0
JCLKO_DCC_DCC10→ G:JVPFS10_DCSMUX_CORE_DCSMUX1
JCLKO_DCC_DCC11→ G:JVPFS11_CMUX_CORE_CMUX0
JCLKO_DCC_DCC11→ G:JVPFS11_CMUX_CORE_CMUX1
JCLKO_DCC_DCC11→ G:JVPFS11_DCSMUX_CORE_DCSMUX0
JCLKO_DCC_DCC11→ G:JVPFS11_DCSMUX_CORE_DCSMUX1
JCLKO_DCC_DCC12→ G:JVPFS12_CMUX_CORE_CMUX0
JCLKO_DCC_DCC12→ G:JVPFS12_CMUX_CORE_CMUX1
JCLKO_DCC_DCC12→ G:JVPFS12_DCSMUX_CORE_DCSMUX0
JCLKO_DCC_DCC12→ G:JVPFS12_DCSMUX_CORE_DCSMUX1
JCLKO_DCC_DCC13→ G:JVPFS13_CMUX_CORE_CMUX0
JCLKO_DCC_DCC13→ G:JVPFS13_CMUX_CORE_CMUX1
JCLKO_DCC_DCC13→ G:JVPFS13_DCSMUX_CORE_DCSMUX0
JCLKO_DCC_DCC13→ G:JVPFS13_DCSMUX_CORE_DCSMUX1
JCLKO_DCC_DCC14→ G:JVPFS14_CMUX_CORE_CMUX0
JCLKO_DCC_DCC14→ G:JVPFS14_CMUX_CORE_CMUX1
JCLKO_DCC_DCC14→ G:JVPFS14_DCSMUX_CORE_DCSMUX0
JCLKO_DCC_DCC14→ G:JVPFS14_DCSMUX_CORE_DCSMUX1
JCLKO_DCC_DCC15→ G:JVPFS15_CMUX_CORE_CMUX0
JCLKO_DCC_DCC15→ G:JVPFS15_CMUX_CORE_CMUX1
JCLKO_DCC_DCC15→ G:JVPFS15_DCSMUX_CORE_DCSMUX0
JCLKO_DCC_DCC15→ G:JVPFS15_DCSMUX_CORE_DCSMUX1
JCLKO_DCC_DCC1→ G:JVPFS1_CMUX_CORE_CMUX0
JCLKO_DCC_DCC1→ G:JVPFS1_CMUX_CORE_CMUX1
JCLKO_DCC_DCC1→ G:JVPFS1_DCSMUX_CORE_DCSMUX0
JCLKO_DCC_DCC1→ G:JVPFS1_DCSMUX_CORE_DCSMUX1
JCLKO_DCC_DCC2→ G:JVPFS2_CMUX_CORE_CMUX0
JCLKO_DCC_DCC2→ G:JVPFS2_CMUX_CORE_CMUX1
JCLKO_DCC_DCC2→ G:JVPFS2_DCSMUX_CORE_DCSMUX0
JCLKO_DCC_DCC2→ G:JVPFS2_DCSMUX_CORE_DCSMUX1
JCLKO_DCC_DCC3→ G:JVPFS3_CMUX_CORE_CMUX0
JCLKO_DCC_DCC3→ G:JVPFS3_CMUX_CORE_CMUX1
JCLKO_DCC_DCC3→ G:JVPFS3_DCSMUX_CORE_DCSMUX0
JCLKO_DCC_DCC3→ G:JVPFS3_DCSMUX_CORE_DCSMUX1
JCLKO_DCC_DCC4→ G:JVPFS4_CMUX_CORE_CMUX0
JCLKO_DCC_DCC4→ G:JVPFS4_CMUX_CORE_CMUX1
JCLKO_DCC_DCC4→ G:JVPFS4_DCSMUX_CORE_DCSMUX0
JCLKO_DCC_DCC4→ G:JVPFS4_DCSMUX_CORE_DCSMUX1
JCLKO_DCC_DCC5→ G:JVPFS5_CMUX_CORE_CMUX0
JCLKO_DCC_DCC5→ G:JVPFS5_CMUX_CORE_CMUX1
JCLKO_DCC_DCC5→ G:JVPFS5_DCSMUX_CORE_DCSMUX0
JCLKO_DCC_DCC5→ G:JVPFS5_DCSMUX_CORE_DCSMUX1
JCLKO_DCC_DCC6→ G:JVPFS6_CMUX_CORE_CMUX0
JCLKO_DCC_DCC6→ G:JVPFS6_CMUX_CORE_CMUX1
JCLKO_DCC_DCC6→ G:JVPFS6_DCSMUX_CORE_DCSMUX0
JCLKO_DCC_DCC6→ G:JVPFS6_DCSMUX_CORE_DCSMUX1
JCLKO_DCC_DCC7→ G:JVPFS7_CMUX_CORE_CMUX0
JCLKO_DCC_DCC7→ G:JVPFS7_CMUX_CORE_CMUX1
JCLKO_DCC_DCC7→ G:JVPFS7_DCSMUX_CORE_DCSMUX0
JCLKO_DCC_DCC7→ G:JVPFS7_DCSMUX_CORE_DCSMUX1
JCLKO_DCC_DCC8→ G:JVPFS8_CMUX_CORE_CMUX0
JCLKO_DCC_DCC8→ G:JVPFS8_CMUX_CORE_CMUX1
JCLKO_DCC_DCC8→ G:JVPFS8_DCSMUX_CORE_DCSMUX0
JCLKO_DCC_DCC8→ G:JVPFS8_DCSMUX_CORE_DCSMUX1
JCLKO_DCC_DCC9→ G:JVPFS9_CMUX_CORE_CMUX0
JCLKO_DCC_DCC9→ G:JVPFS9_CMUX_CORE_CMUX1
JCLKO_DCC_DCC9→ G:JVPFS9_DCSMUX_CORE_DCSMUX0
JCLKO_DCC_DCC9→ G:JVPFS9_DCSMUX_CORE_DCSMUX1
S1:JCIBMUXOUTC0→ JCE_DCC_DCC0
S1:JCIBMUXOUTC1→ JCE_DCC_DCC1
S1E1:JCIBMUXOUTC2→ JCE_DCC_DCC10
S1E1:JCIBMUXOUTC3→ JCE_DCC_DCC11
S1E1:JCIBMUXOUTC4→ JCE_DCC_DCC12
S1E1:JCIBMUXOUTC5→ JCE_DCC_DCC13
S1E1:JCIBMUXOUTC6→ JCE_DCC_DCC14
S1E1:JCIBMUXOUTC7→ JCE_DCC_DCC15
S1:JCIBMUXOUTC2→ JCE_DCC_DCC2
S1:JCIBMUXOUTC3→ JCE_DCC_DCC3
S1:JCIBMUXOUTC4→ JCE_DCC_DCC4
S1:JCIBMUXOUTC5→ JCE_DCC_DCC5
S1:JCIBMUXOUTC6→ JCE_DCC_DCC6
S1:JCIBMUXOUTC7→ JCE_DCC_DCC7
S1E1:JCIBMUXOUTC0→ JCE_DCC_DCC8
S1E1:JCIBMUXOUTC1→ JCE_DCC_DCC9
G:JVPFS0_TMID_CORE_TMIDMUX→ JCLKI_DCC_DCC0
G:JVPFS1_TMID_CORE_TMIDMUX→ JCLKI_DCC_DCC1
G:JVPFS10_TMID_CORE_TMIDMUX→ JCLKI_DCC_DCC10
G:JVPFS11_TMID_CORE_TMIDMUX→ JCLKI_DCC_DCC11
G:JVPFS12_TMID_CORE_TMIDMUX→ JCLKI_DCC_DCC12
G:JVPFS13_TMID_CORE_TMIDMUX→ JCLKI_DCC_DCC13
G:JVPFS14_TMID_CORE_TMIDMUX→ JCLKI_DCC_DCC14
G:JVPFS15_TMID_CORE_TMIDMUX→ JCLKI_DCC_DCC15
G:JVPFS2_TMID_CORE_TMIDMUX→ JCLKI_DCC_DCC2
G:JVPFS3_TMID_CORE_TMIDMUX→ JCLKI_DCC_DCC3
G:JVPFS4_TMID_CORE_TMIDMUX→ JCLKI_DCC_DCC4
G:JVPFS5_TMID_CORE_TMIDMUX→ JCLKI_DCC_DCC5
G:JVPFS6_TMID_CORE_TMIDMUX→ JCLKI_DCC_DCC6
G:JVPFS7_TMID_CORE_TMIDMUX→ JCLKI_DCC_DCC7
G:JVPFS8_TMID_CORE_TMIDMUX→ JCLKI_DCC_DCC8
G:JVPFS9_TMID_CORE_TMIDMUX→ JCLKI_DCC_DCC9
JCLKI_DCC_DCC0→ JCLKO_DCC_DCC0
JCLKI_DCC_DCC1→ JCLKO_DCC_DCC1
JCLKI_DCC_DCC10→ JCLKO_DCC_DCC10
JCLKI_DCC_DCC11→ JCLKO_DCC_DCC11
JCLKI_DCC_DCC12→ JCLKO_DCC_DCC12
JCLKI_DCC_DCC13→ JCLKO_DCC_DCC13
JCLKI_DCC_DCC14→ JCLKO_DCC_DCC14
JCLKI_DCC_DCC15→ JCLKO_DCC_DCC15
JCLKI_DCC_DCC2→ JCLKO_DCC_DCC2
JCLKI_DCC_DCC3→ JCLKO_DCC_DCC3
JCLKI_DCC_DCC4→ JCLKO_DCC_DCC4
JCLKI_DCC_DCC5→ JCLKO_DCC_DCC5
JCLKI_DCC_DCC6→ JCLKO_DCC_DCC6
JCLKI_DCC_DCC7→ JCLKO_DCC_DCC7
JCLKI_DCC_DCC8→ JCLKO_DCC_DCC8
JCLKI_DCC_DCC9→ JCLKO_DCC_DCC9