SYSIO_B3_0_DLY30_V18 Tile Documentation

Tile Bels

NameType
PIOA SEIO18_CORE
PIOB SEIO18_CORE
DIFFIO18 DIFFIO18_CORE

Config Bitmap

 
 
 
 
 
C
C
C
C
L
L
L
L
M
 
R
T
M
 
D
I
I
D
D
D
D
S
 
 
 
I
O
S
G
 
D
S
S
D
R
 
D
E
V
V
V
V
V
V
V
N
 
D
D
D
R
R
R
R
 
 
M
 
D
R
D
D
D
M
 
 
 
 
 
 
T
P
P
V
V
V
D
I
I
D
L
T
1
 
 
S
S
S
 
 
 
 
 
 
S
T
I
L
S
D
L
T
T
T
T
1
1
1
1
1
H
1
H
H
H
O
D
 
V
 
 
 
 
 
 
D
S
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
8
 
 
A
 
A
A
A
A
 
A
A
A
A
 
A
 
 
 
 
C
I
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
U
 
 
 
 
 
 
 
 
 
 
 

Routing Muxes

Mux driving JECLKOUT_I217

Source F20B0 F21B0
JECLKIN0_I217 - -
JECLKIN1_I217 - 1
JECLKIN2_I217 1 -
JECLKIN3_I217 1 1

Mux driving N1:JCLKOUT_DLLDEL_CORE_I0

Source F75B1
N1:JCLKIN_DLLDEL_CORE_I0 1

Mux driving N1:JZ_I4_0

Source F54B1
G:JD0_I4_0 -
G:JD1_I4_0 1

Mux driving N1:JZ_I4_1

Source F54B1
G:JD0_I4_1 -
G:JD1_I4_1 1

Mux driving N1:JZ_I4_2

Source F54B1
G:JD0_I4_2 -
G:JD1_I4_2 1

Mux driving N1:JZ_I4_3

Source F54B1
G:JD0_I4_3 -
G:JD1_I4_3 1

Mux driving N1:JZ_I4_4

Source F54B1
G:JD0_I4_4 -
G:JD1_I4_4 1

Mux driving N1:JZ_I4_5

Source F54B1
G:JD0_I4_5 -
G:JD1_I4_5 1

Mux driving N1:JZ_I4_6

Source F54B1
G:JD0_I4_6 -
G:JD1_I4_6 1

Mux driving N1:JZ_I4_7

Source F54B1
G:JD0_I4_7 -
G:JD1_I4_7 1

Mux driving N1:JZ_I4_8

Source F54B1
G:JD0_I4_8 -
G:JD1_I4_8 1

Configuration Words

Configuration word DLLDEL30.ADJUST

DLLDEL30.ADJUST[0]F69B1
DLLDEL30.ADJUST[1]F67B1
DLLDEL30.ADJUST[2]F66B1
DLLDEL30.ADJUST[3]F65B1
DLLDEL30.ADJUST[4]F64B1
DLLDEL30.ADJUST[5]F62B1
DLLDEL30.ADJUST[6]F61B1
DLLDEL30.ADJUST[7]F60B1
DLLDEL30.ADJUST[8]F59B1

Configuration word IOLOGICA.DELAY.DEL_VALUE

initial fine delay value

IOLOGICA.DELAY.DEL_VALUE[0]F43B0
IOLOGICA.DELAY.DEL_VALUE[1]F44B0
IOLOGICA.DELAY.DEL_VALUE[2]F45B0
IOLOGICA.DELAY.DEL_VALUE[3]F46B0
IOLOGICA.DELAY.DEL_VALUE[4]F47B0
IOLOGICA.DELAY.DEL_VALUE[5]F48B0
IOLOGICA.DELAY.DEL_VALUE[6]F49B0

Configuration Enums

Configuration enum BANK3.VREF1_USED

use VREF1 input for bank 3

Value F94B1
OFF -
ON 1

Configuration enum DLLDEL30.CLKINMUX

Value F74B1
CLKIN -
INV 1

Configuration enum DLLDEL30.DEL_ADJUST

Value F57B1
MINUS 1
PLUS -

Configuration enum DLLDEL30.ENABLE

DLLDEL primitive mode

Value F75B1
DISABLED -
ENABLED 1

Configuration enum IOLOGICA.CEINMUX

Value F6B0 F7B0
1 - 1
CEIN 1 -
INV - -

Configuration enum IOLOGICA.CEOUTMUX

Value F5B0 F8B0
1 - 1
CEOUT 1 -
INV - -

Configuration enum IOLOGICA.DELAY.COARSE_DELAY

Value F52B0 F53B0
0NS - -
0P8NS 1 -
1P6NS - 1

Configuration enum IOLOGICA.DELAY.EDGE_MONITOR

Value F17B0
DISABLED -
ENABLED 1

Configuration enum IOLOGICA.DELAY.WAIT_FOR_EDGE

Value F42B0
DISABLED -
ENABLED 1

Configuration enum IOLOGICA.DELAYMUX

Value F35B0
IN -
OUT_REG 1

Configuration enum IOLOGICA.DIRMUX

Value F54B0
0 -
DIR 1

Configuration enum IOLOGICA.GSR

Value F33B0
DISABLED 1
ENABLED -

Configuration enum IOLOGICA.IDDRX1_ODDRX1.OUTPUT

Value F22B0
DISABLED -
ENABLED 1

Configuration enum IOLOGICA.IDDRXN.DDRMODE

Value F66B0 F67B0 F68B0
IDDR71 - 1 1
IDDRX2 - 1 -
IDDRX4 1 - -
IDDRX5 1 - 1
NONE - - -

Configuration enum IOLOGICA.INMUX

Value F30B0
BYPASS -
DELAY 1

Configuration enum IOLOGICA.INREG.REGSET

Value F15B0
RESET -
SET 1

Configuration enum IOLOGICA.IREG_OREG.OUTPUT

Value F23B0
DISABLED -
ENABLED 1

Configuration enum IOLOGICA.LOAD_NMUX

Value F50B0
1 -
LOAD_N 1

Configuration enum IOLOGICA.LSRINMUX

Value F9B0 F10B0
0 - -
INV - 1
LSRIN 1 1

Configuration enum IOLOGICA.LSROUTMUX

Value F11B0 F12B0
0 - -
INV 1 -
LSROUT 1 1

Configuration enum IOLOGICA.MIDDRXN.DDRMODE

Value F65B0 F66B0 F67B0
MIDDRX2 1 - 1
MIDDRX4 1 1 -
NONE - - -

Configuration enum IOLOGICA.MODDRXN.DDRMODE

Value F22B0 F23B0 F24B0 F24B1 F25B0 F38B0 F41B0 F63B0
MODDRX2_DQSW 1 1 - - - 1 1 -
MODDRX2_DQSW270 1 1 - - - - 1 1
MODDRX4_DQSW 1 1 - 1 - 1 1 -
MODDRX4_DQSW270 1 1 - 1 - - 1 1
MOSHX2 1 1 1 - - - - 1
MOSHX4 1 1 1 - 1 - - 1
NONE - - - - - - - -

Configuration enum IOLOGICA.MODE

Value F13B0 F68B0
IDDRX1_ODDRX1 - 1
IDDRXN - -
IREG_OREG - -
MIDDRXN_MODDRXN 1 -
NONE - -
ODDRXN - -

Configuration enum IOLOGICA.MOVEMUX

Value F61B0
0 -
MOVE 1

Configuration enum IOLOGICA.MTDDRXN.DDRMODE

Value F19B0
MTSHX2 1
MTSHX4 1
NONE -

Configuration enum IOLOGICA.ODDRXN.DDRMODE

Value F22B0 F23B0 F24B1 F25B0 F63B0
NONE - - - - -
ODDR71 1 1 - 1 1
ODDRX2 1 1 - - 1
ODDRX4 1 1 1 - 1
ODDRX5 1 1 1 1 1

Configuration enum IOLOGICA.OUTMUX

Value F31B0
BYPASS -
DELAY 1

Configuration enum IOLOGICA.OUTREG.REGSET

Value F64B0
RESET -
SET 1

Configuration enum IOLOGICA.RANK0UPDATEMUX

Value F55B0
OFF -
RANK0UPDATE 1

Configuration enum IOLOGICA.RANK1UPDATEMUX

Value F58B0
OFF -
RANK1UPDATE 1

Configuration enum IOLOGICA.RANKENABLEMUX

Value F56B0
OFF -
RANKENABLE 1

Configuration enum IOLOGICA.RANKSELECTMUX

Value F57B0
OFF -
RANKSELECT 1

Configuration enum IOLOGICA.SCLKINMUX

Value F25B1 F26B0
0 - -
INV 1 1
SCLKIN 1 -

Configuration enum IOLOGICA.SCLKOUTMUX

Value F36B0 F37B0
0 - -
INV 1 1
SCLKOUT 1 -

Configuration enum IOLOGICA.SRMODE

Value F32B0
ASYNC -
LSR_OVER_CE 1

Configuration enum IOLOGICA.TSREG.REGSET

Value F39B0
RESET -
SET 1

Configuration enum PIOA.DIFFIO18.BASE_TYPE

Value F0B1 F1B1 F2B1 F3B1 F9B1 F10B1 F11B1 F13B1 F15B1 F16B0 F17B1 F77B0 F78B0 F100B0
BIDIR_HSTL15D_I 1 1 - - - 1 - 1 - - 1 - 1 -
BIDIR_HSUL12D 1 1 - - - 1 - 1 - - 1 - 1 -
BIDIR_LVDS 1 1 - - - - - 0 - - 1 - 1 -
BIDIR_MIPI_DPHY 1 1 - - - - - 0 - 1 1 - 1 1
BIDIR_SLVS 1 1 - - - - - 0 - - 1 - 1 1
BIDIR_SSTL135D_I 1 1 - - - - 1 1 - - 1 - 1 -
BIDIR_SSTL135D_II 1 1 - - - - - 0 - - 1 - 1 -
BIDIR_SSTL15D_I 1 1 - - - - 1 1 - - 1 - 1 -
BIDIR_SSTL15D_II 1 1 - - - - - 0 - - 1 - 1 -
INPUT_HSTL15D_I - - 1 - - - - 0 - - 1 - 1 -
INPUT_HSUL12D - - 1 - - - - 0 - - 1 - 1 -
INPUT_LVDS - - 1 - - - - 0 - - 1 - 1 -
INPUT_MIPI_DPHY - - 1 - - - - 0 1 1 1 - 1 1
INPUT_SLVS - - 1 - - - - 0 - - 1 - 1 1
INPUT_SSTL135D_I - - 1 - - - - 0 - - 1 - 1 -
INPUT_SSTL135D_II - - 1 - - - - 0 - - 1 - 1 -
INPUT_SSTL15D_I - - 1 - - - - 0 - - 1 - 1 -
INPUT_SSTL15D_II - - 1 - - - - 0 - - 1 - 1 -
INPUT_SUBLVDS - - 1 - - - - 0 - - 1 - 1 -
NONE - - - - - - - - - - - - - -
OUTPUT_HSTL15D_I 1 1 1 1 - 1 - 1 - - 1 1 - -
OUTPUT_HSUL12D 1 1 1 1 - 1 - 1 - - 1 1 - -
OUTPUT_LVDS 1 1 1 1 - - - 0 - - 1 1 - -
OUTPUT_MIPI_DPHY 1 1 1 1 - - - 0 - 1 1 1 - -
OUTPUT_SLVS 1 1 1 1 - - - 0 - - 1 1 - -
OUTPUT_SSTL135D_I 1 1 1 1 - - 1 1 - - 1 1 - -
OUTPUT_SSTL135D_II 1 1 1 1 - - - 0 - - 1 1 - -
OUTPUT_SSTL15D_I 1 1 1 1 - - 1 1 - - 1 1 - -
OUTPUT_SSTL15D_II 1 1 1 1 - - - 0 - - 1 1 - -
OUTPUT_SUBLVDSEH 1 1 1 1 1 1 1 1 - - 1 1 - -

Configuration enum PIOA.DIFFIO18.DIFFDRIVE_LVDS

Value F102B0
3P5 1
NA -

Configuration enum PIOA.DIFFIO18.DIFFDRIVE_MIPI_DPHY

Value F15B1 F84B0 F103B0
2P0 1 1 1
NA - - -

Configuration enum PIOA.DIFFIO18.DIFFDRIVE_SLVS

Value F103B0
2P0 1
NA -

Configuration enum PIOA.DIFFIO18.DIFFRESISTOR

Value F104B0
100 1
OFF 0

Configuration enum PIOA.DIFFIO18.DIFFRX_INV

Value F82B0
INVERT 1
NORMAL -

Configuration enum PIOA.DIFFIO18.DIFFTX_INV

Value F101B0
INVERT 1
NORMAL -

Configuration enum PIOA.DIFFIO18.PULLMODE

Value F76B0
FAILSAFE 1
NONE 0

Configuration enum PIOA.SEIO18.BASE_TYPE

Value F0B1 F1B1 F2B1 F3B1 F10B1 F11B1 F13B1 F17B1 F75B0 F77B0 F86B0
BIDIR_HSTL15_I 1 1 - - 1 - 1 - - - -
BIDIR_HSUL12 1 1 - - 1 - 1 - - - -
BIDIR_LVCMOS10H 1 1 - - 1 - 1 1 1 - 1
BIDIR_LVCMOS12H 1 1 - - 1 - 1 1 1 - -
BIDIR_LVCMOS15H 1 1 - - 1 - 1 - - - -
BIDIR_LVCMOS18H 1 1 - - 1 - 1 - - - -
BIDIR_SSTL135_I 1 1 - - - 1 1 - - - -
BIDIR_SSTL135_II 1 1 - - - - - - - - -
BIDIR_SSTL15_I 1 1 - - - 1 1 - - - -
BIDIR_SSTL15_II 1 1 - - - - - - - - -
INPUT_HSTL15_I - - 1 - - - - - - - -
INPUT_HSUL12 - - 1 - - - - - - - -
INPUT_LVCMOS10H - - 1 - - - - 1 1 - 1
INPUT_LVCMOS10R - - 1 - - - - - - - -
INPUT_LVCMOS12H - - 1 - - - - 1 1 - -
INPUT_LVCMOS15H - - 1 - - - - - - - -
INPUT_LVCMOS18H - - 1 - - - - - - - -
INPUT_SSTL135_I - - 1 - - - - - - - -
INPUT_SSTL135_II - - 1 - - - - - - - -
INPUT_SSTL15_I - - 1 - - - - - - - -
INPUT_SSTL15_II - - 1 - - - - - - - -
NONE - - - - - - 1 - - - -
OUTPUT_HSTL15_I 1 1 1 1 1 - 1 1 - 1 -
OUTPUT_HSUL12 1 1 1 1 1 - 1 1 - 1 -
OUTPUT_LVCMOS10H 1 1 1 1 1 - 1 1 - 1 -
OUTPUT_LVCMOS12H 1 1 1 1 1 - 1 1 - 1 -
OUTPUT_LVCMOS15H 1 1 1 1 1 - 1 1 - 1 -
OUTPUT_LVCMOS18H 1 1 1 1 1 - 1 1 - 1 -
OUTPUT_SSTL135_I 1 1 1 1 - 1 1 1 - 1 -
OUTPUT_SSTL135_II 1 1 1 1 - - - 1 - 1 -
OUTPUT_SSTL15_I 1 1 1 1 - 1 1 1 - 1 -
OUTPUT_SSTL15_II 1 1 1 1 - - - 1 - 1 -

Configuration enum PIOA.SEIO18.DFTDO2DI

Value F81B0
DISABLED -
ENABLED 1

Configuration enum PIOA.SEIO18.DRIVE_1V0

Value F9B1 F10B1 F11B1 F12B1
2 1 0 1 0
4 0 1 0 1

Configuration enum PIOA.SEIO18.DRIVE_1V2

Value F9B1 F10B1 F11B1 F12B1 F13B1
2 1 0 1 0 0
4 0 1 0 1 0
8 0 1 0 0 1

Configuration enum PIOA.SEIO18.DRIVE_1V5

Value F9B1 F10B1 F11B1 F12B1 F13B1
2 1 0 1 0 0
4 0 1 0 1 0
8 0 1 0 0 1

Configuration enum PIOA.SEIO18.DRIVE_1V8

Value F9B1 F10B1 F11B1 F12B1 F13B1
12 1 1 1 0 1
2 1 0 1 0 0
4 0 1 0 1 0
50RS 0 1 0 0 1
8 0 1 0 0 1

Configuration enum PIOA.SEIO18.DRIVE_HSUL12

Value F9B1 F11B1 F12B1 F13B1
4 0 0 1 0
6 1 1 1 0
8 0 0 0 1

Configuration enum PIOA.SEIO18.ENADC_IN

Value F83B0
DISABLED -
ENABLED 1

Configuration enum PIOA.SEIO18.INT_LPBK

Value F105B0
DISABLED -
ENABLED 1

Configuration enum PIOA.SEIO18.LOOPBKCD2AB

Value F85B0
DISABLED -
ENABLED 1

Configuration enum PIOA.SEIO18.OPENDRAIN

Value F14B1
OFF -
ON 1

Configuration enum PIOA.SEIO18.PULLMODE

Value F76B0 F77B0
DOWN 0 0
KEEPER 1 0
NONE 0 1
UP 1 1

Configuration enum PIOA.SEIO18.SLEEPHIGHLEAKAGE

Value F99B0
DISABLED -
ENABLED 1

Configuration enum PIOA.SEIO18.SLEWRATE

Value F90B0 F91B0 F92B0
FAST 1 1 1
MED 1 0 0
SLOW 0 0 0

Configuration enum PIOA.SEIO18.TERMINATION_1V2

Value F5B1 F6B1 F7B1 F8B1
40 - - - 1
50 - 1 1 -
60 - - 1 -
75 1 1 - -
OFF - - - -

Configuration enum PIOA.SEIO18.TERMINATION_1V35

Value F4B1 F5B1 F6B1 F7B1 F8B1
40 - 1 - - 1
50 1 - 1 1 -
60 - - - 1 -
75 - 1 1 - -
OFF - - - - -

Configuration enum PIOA.SEIO18.TERMINATION_1V5

Value F4B1 F5B1 F6B1 F7B1 F8B1
40 - 1 - - 1
50 1 - 1 1 -
60 - - - 1 -
75 - 1 1 - -
OFF - - - - -

Configuration enum PIOA.SEIO18.TERMINATION_1V8

Value F4B1 F5B1 F6B1 F7B1 F8B1
150 - - 1 - -
40 - - 1 - 1
50 - 1 1 1 -
60 - 1 - 1 -
75 1 1 1 - -
OFF - - - - -

Configuration enum PIOA.SEIO18.UNDERDRIVE_1V8

Value F87B0
OFF 0
ON 1

Configuration enum PIOA.SEIO18.VREF

Value F17B1 F78B0 F79B0 F80B0
OFF - - - -
VREF1_LOAD 1 1 1 -
VREF2_LOAD 1 1 - 1

Configuration enum PIOA.TMUX

Value F3B1
INV 1
T -

Fixed Connections

SourceSink
N1:JCLKOUT_DLLDEL_CORE_I0→ G:JPCLKT0_ECLKBANK_CORE_ECLKBANK3
N1:JCLKOUT_DLLDEL_CORE_I0→ G:JPCLKT30_BMID_CORE_BMIDMUX
N1:JCE0→ JCEIN_IOLOGIC_CORE_I_GEARING_PIC_TOP_A
N1E1:JCE0→ JCEIN_IOLOGIC_CORE_I_GEARING_PIC_TOP_B
N1:JCE0→ JCEOUT_IOLOGIC_CORE_I_GEARING_PIC_TOP_A
N1E1:JCE0→ JCEOUT_IOLOGIC_CORE_I_GEARING_PIC_TOP_B
N1:JCIBMUXOUTC5→ JCIBCRS0_IOLOGIC_CORE_I_GEARING_PIC_TOP_A
N1E1:JCIBMUXOUTC5→ JCIBCRS0_IOLOGIC_CORE_I_GEARING_PIC_TOP_B
N1:JCIBMUXOUTD5→ JCIBCRS1_IOLOGIC_CORE_I_GEARING_PIC_TOP_A
N1E1:JCIBMUXOUTD5→ JCIBCRS1_IOLOGIC_CORE_I_GEARING_PIC_TOP_B
N1:JCIBMUXOUTB6→ JCIBTSTSG_IOLOGIC_CORE_I_GEARING_PIC_TOP_A
N1E1:JCIBMUXOUTB6→ JCIBTSTSG_IOLOGIC_CORE_I_GEARING_PIC_TOP_B
N1:JCIBMUXOUTA2→ JDIR_IOLOGIC_CORE_I_GEARING_PIC_TOP_A
N1E1:JCIBMUXOUTA2→ JDIR_IOLOGIC_CORE_I_GEARING_PIC_TOP_B
JPADDI_DIFFIO18_CORE_IOA→ JDI_IOLOGIC_CORE_I_GEARING_PIC_TOP_A
JPADDI_SEIO18_CORE_IOB→ JDI_IOLOGIC_CORE_I_GEARING_PIC_TOP_B
N1:JCIBMUXOUTB7→ JDOLP_DIFFIO18_CORE_IOA
JDOLP_IOLOGIC_CORE_I_GEARING_PIC_TOP_A→ JDOLP_DIFFIO18_CORE_IOA
N1E1:JCIBMUXOUTB7→ JDOLP_SEIO18_CORE_IOB
JDOLP_IOLOGIC_CORE_I_GEARING_PIC_TOP_B→ JDOLP_SEIO18_CORE_IOB
JTXDATA0_IOLOGIC_CORE_I_GEARING_PIC_TOP_A→ JDOUT_IOLOGIC_CORE_I_GEARING_PIC_TOP_A
JTXDATA0_IOLOGIC_CORE_I_GEARING_PIC_TOP_B→ JDOUT_IOLOGIC_CORE_I_GEARING_PIC_TOP_B
DQSG:JDQSR90_DQSBUF_CORE_I_DQS_TOP→ JDQSR90_IOLOGIC_CORE_I_GEARING_PIC_TOP_A
DQSG:JDQSR90_DQSBUF_CORE_I_DQS_TOP→ JDQSR90_IOLOGIC_CORE_I_GEARING_PIC_TOP_B
DQSG:JDQSW270_DQSBUF_CORE_I_DQS_TOP→ JDQSW270_IOLOGIC_CORE_I_GEARING_PIC_TOP_A
DQSG:JDQSW270_DQSBUF_CORE_I_DQS_TOP→ JDQSW270_IOLOGIC_CORE_I_GEARING_PIC_TOP_B
DQSG:JDQSW_DQSBUF_CORE_I_DQS_TOP→ JDQSW_IOLOGIC_CORE_I_GEARING_PIC_TOP_A
DQSG:JDQSW_DQSBUF_CORE_I_DQS_TOP→ JDQSW_IOLOGIC_CORE_I_GEARING_PIC_TOP_B
G:JECLKOUT0_ECLKCASMUX_CORE_ECLKCASMUX3→ JECLKIN0_I217
G:JECLKOUT0_ECLKCASMUX_CORE_ECLKCASMUX3→ JECLKIN0_I218
G:JECLKOUT1_ECLKCASMUX_CORE_ECLKCASMUX3→ JECLKIN1_I217
G:JECLKOUT1_ECLKCASMUX_CORE_ECLKCASMUX3→ JECLKIN1_I218
G:JECLKOUT2_ECLKCASMUX_CORE_ECLKCASMUX3→ JECLKIN2_I217
G:JECLKOUT2_ECLKCASMUX_CORE_ECLKCASMUX3→ JECLKIN2_I218
G:JECLKOUT3_ECLKCASMUX_CORE_ECLKCASMUX3→ JECLKIN3_I217
G:JECLKOUT3_ECLKCASMUX_CORE_ECLKCASMUX3→ JECLKIN3_I218
JECLKOUT_I217→ JECLK_IOLOGIC_CORE_I_GEARING_PIC_TOP_A
JECLKOUT_I218→ JECLK_IOLOGIC_CORE_I_GEARING_PIC_TOP_B
N1:JCIBMUXOUTB4→ JHSRXEN_DIFFIO18_CORE_IOA
N1:JCIBMUXOUTD4→ JHSTXEN_DIFFIO18_CORE_IOA
JDI_IOLOGIC_CORE_I_GEARING_PIC_TOP_A→ JINDD_IOLOGIC_CORE_I_GEARING_PIC_TOP_A
JDI_IOLOGIC_CORE_I_GEARING_PIC_TOP_B→ JINDD_IOLOGIC_CORE_I_GEARING_PIC_TOP_B
JINLP_DIFFIO18_CORE_IOA→ JINLP_IOLOGIC_CORE_I_GEARING_PIC_TOP_A
JINLP_SEIO18_CORE_IOB→ JINLP_IOLOGIC_CORE_I_GEARING_PIC_TOP_B
N1:JCIBMUXOUTC2→ JLOAD_N_IOLOGIC_CORE_I_GEARING_PIC_TOP_A
N1E1:JCIBMUXOUTC2→ JLOAD_N_IOLOGIC_CORE_I_GEARING_PIC_TOP_B
N1:JLSR0→ JLSRIN_IOLOGIC_CORE_I_GEARING_PIC_TOP_A
N1E1:JLSR0→ JLSRIN_IOLOGIC_CORE_I_GEARING_PIC_TOP_B
N1:JLSR0→ JLSROUT_IOLOGIC_CORE_I_GEARING_PIC_TOP_A
N1E1:JLSR0→ JLSROUT_IOLOGIC_CORE_I_GEARING_PIC_TOP_B
N1:JCIBMUXOUTB2→ JMOVE_IOLOGIC_CORE_I_GEARING_PIC_TOP_A
N1E1:JCIBMUXOUTB2→ JMOVE_IOLOGIC_CORE_I_GEARING_PIC_TOP_B
N1:JCIBMUXOUTA0→ JPADDO_DIFFIO18_CORE_IOA
JDOUT_IOLOGIC_CORE_I_GEARING_PIC_TOP_A→ JPADDO_DIFFIO18_CORE_IOA
N1E1:JCIBMUXOUTA0→ JPADDO_SEIO18_CORE_IOB
JDOUT_IOLOGIC_CORE_I_GEARING_PIC_TOP_B→ JPADDO_SEIO18_CORE_IOB
N1:JCIBMUXOUTB0→ JPADDT_DIFFIO18_CORE_IOA
JTOUT_IOLOGIC_CORE_I_GEARING_PIC_TOP_A→ JPADDT_DIFFIO18_CORE_IOA
N1E1:JCIBMUXOUTB0→ JPADDT_SEIO18_CORE_IOB
JTOUT_IOLOGIC_CORE_I_GEARING_PIC_TOP_B→ JPADDT_SEIO18_CORE_IOB
N1:JCIBMUXOUTC6→ JRANK0UPDATE_IOLOGIC_CORE_I_GEARING_PIC_TOP_A
N1E1:JCIBMUXOUTC6→ JRANK0UPDATE_IOLOGIC_CORE_I_GEARING_PIC_TOP_B
N1:JCIBMUXOUTD6→ JRANK1UPDATE_IOLOGIC_CORE_I_GEARING_PIC_TOP_A
N1E1:JCIBMUXOUTD6→ JRANK1UPDATE_IOLOGIC_CORE_I_GEARING_PIC_TOP_B
N1:JCIBMUXOUTA7→ JRANKENABLE_IOLOGIC_CORE_I_GEARING_PIC_TOP_A
N1E1:JCIBMUXOUTA7→ JRANKENABLE_IOLOGIC_CORE_I_GEARING_PIC_TOP_B
N1:JCIBMUXOUTA6→ JRANKSELECT_IOLOGIC_CORE_I_GEARING_PIC_TOP_A
N1E1:JCIBMUXOUTA6→ JRANKSELECT_IOLOGIC_CORE_I_GEARING_PIC_TOP_B
DQSG:JRDPNTR0_DQSBUF_CORE_I_DQS_TOP→ JRDPNTR0_IOLOGIC_CORE_I_GEARING_PIC_TOP_A
DQSG:JRDPNTR0_DQSBUF_CORE_I_DQS_TOP→ JRDPNTR0_IOLOGIC_CORE_I_GEARING_PIC_TOP_B
DQSG:JRDPNTR1_DQSBUF_CORE_I_DQS_TOP→ JRDPNTR1_IOLOGIC_CORE_I_GEARING_PIC_TOP_A
DQSG:JRDPNTR1_DQSBUF_CORE_I_DQS_TOP→ JRDPNTR1_IOLOGIC_CORE_I_GEARING_PIC_TOP_B
DQSG:JRDPNTR2_DQSBUF_CORE_I_DQS_TOP→ JRDPNTR2_IOLOGIC_CORE_I_GEARING_PIC_TOP_A
DQSG:JRDPNTR2_DQSBUF_CORE_I_DQS_TOP→ JRDPNTR2_IOLOGIC_CORE_I_GEARING_PIC_TOP_B
N1:JCLK0→ JSCLKIN_IOLOGIC_CORE_I_GEARING_PIC_TOP_A
N1E1:JCLK0→ JSCLKIN_IOLOGIC_CORE_I_GEARING_PIC_TOP_B
N1:JCLK0→ JSCLKOUT_IOLOGIC_CORE_I_GEARING_PIC_TOP_A
N1E1:JCLK0→ JSCLKOUT_IOLOGIC_CORE_I_GEARING_PIC_TOP_B
N1:JCIBMUXOUTB7→ JTDOLP_IOLOGIC_CORE_I_GEARING_PIC_TOP_A
N1E1:JCIBMUXOUTB7→ JTDOLP_IOLOGIC_CORE_I_GEARING_PIC_TOP_B
JTSDATA0_IOLOGIC_CORE_I_GEARING_PIC_TOP_A→ JTOUT_IOLOGIC_CORE_I_GEARING_PIC_TOP_A
JTSDATA0_IOLOGIC_CORE_I_GEARING_PIC_TOP_B→ JTOUT_IOLOGIC_CORE_I_GEARING_PIC_TOP_B
N1:JCIBMUXOUTB0→ JTSDATA0_IOLOGIC_CORE_I_GEARING_PIC_TOP_A
N1E1:JCIBMUXOUTB0→ JTSDATA0_IOLOGIC_CORE_I_GEARING_PIC_TOP_B
N1:JCIBMUXOUTC1→ JTSDATA1_IOLOGIC_CORE_I_GEARING_PIC_TOP_A
N1E1:JCIBMUXOUTC1→ JTSDATA1_IOLOGIC_CORE_I_GEARING_PIC_TOP_B
N1:JCIBMUXOUTB3→ JTSDATA2_IOLOGIC_CORE_I_GEARING_PIC_TOP_A
N1E1:JCIBMUXOUTB3→ JTSDATA2_IOLOGIC_CORE_I_GEARING_PIC_TOP_B
N1:JCIBMUXOUTC4→ JTSDATA3_IOLOGIC_CORE_I_GEARING_PIC_TOP_A
N1E1:JCIBMUXOUTC4→ JTSDATA3_IOLOGIC_CORE_I_GEARING_PIC_TOP_B
N1:JCIBMUXOUTA0→ JTXDATA0_IOLOGIC_CORE_I_GEARING_PIC_TOP_A
N1E1:JCIBMUXOUTA0→ JTXDATA0_IOLOGIC_CORE_I_GEARING_PIC_TOP_B
N1:JCIBMUXOUTC0→ JTXDATA1_IOLOGIC_CORE_I_GEARING_PIC_TOP_A
N1E1:JCIBMUXOUTC0→ JTXDATA1_IOLOGIC_CORE_I_GEARING_PIC_TOP_B
N1:JCIBMUXOUTD0→ JTXDATA2_IOLOGIC_CORE_I_GEARING_PIC_TOP_A
N1E1:JCIBMUXOUTD0→ JTXDATA2_IOLOGIC_CORE_I_GEARING_PIC_TOP_B
N1:JCIBMUXOUTA1→ JTXDATA3_IOLOGIC_CORE_I_GEARING_PIC_TOP_A
N1E1:JCIBMUXOUTA1→ JTXDATA3_IOLOGIC_CORE_I_GEARING_PIC_TOP_B
N1:JCIBMUXOUTA5→ JTXDATA4_IOLOGIC_CORE_I_GEARING_PIC_TOP_A
N1E1:JCIBMUXOUTA5→ JTXDATA4_IOLOGIC_CORE_I_GEARING_PIC_TOP_B
N1:JCIBMUXOUTA3→ JTXDATA5_IOLOGIC_CORE_I_GEARING_PIC_TOP_A
N1E1:JCIBMUXOUTA3→ JTXDATA5_IOLOGIC_CORE_I_GEARING_PIC_TOP_B
N1:JCIBMUXOUTC3→ JTXDATA6_IOLOGIC_CORE_I_GEARING_PIC_TOP_A
N1E1:JCIBMUXOUTC3→ JTXDATA6_IOLOGIC_CORE_I_GEARING_PIC_TOP_B
N1:JCIBMUXOUTD3→ JTXDATA7_IOLOGIC_CORE_I_GEARING_PIC_TOP_A
N1E1:JCIBMUXOUTD3→ JTXDATA7_IOLOGIC_CORE_I_GEARING_PIC_TOP_B
N1:JCIBMUXOUTA4→ JTXDATA8_IOLOGIC_CORE_I_GEARING_PIC_TOP_A
N1E1:JCIBMUXOUTA4→ JTXDATA8_IOLOGIC_CORE_I_GEARING_PIC_TOP_B
N1:JCIBMUXOUTB5→ JTXDATA9_IOLOGIC_CORE_I_GEARING_PIC_TOP_A
N1E1:JCIBMUXOUTB5→ JTXDATA9_IOLOGIC_CORE_I_GEARING_PIC_TOP_B
N1:JCIBMUXOUTB1→ JWORDALIGN_IOLOGIC_CORE_I_GEARING_PIC_TOP_A
N1E1:JCIBMUXOUTB1→ JWORDALIGN_IOLOGIC_CORE_I_GEARING_PIC_TOP_B
DQSG:JWRPNTR0_DQSBUF_CORE_I_DQS_TOP→ JWRPNTR0_IOLOGIC_CORE_I_GEARING_PIC_TOP_A
DQSG:JWRPNTR0_DQSBUF_CORE_I_DQS_TOP→ JWRPNTR0_IOLOGIC_CORE_I_GEARING_PIC_TOP_B
DQSG:JWRPNTR1_DQSBUF_CORE_I_DQS_TOP→ JWRPNTR1_IOLOGIC_CORE_I_GEARING_PIC_TOP_A
DQSG:JWRPNTR1_DQSBUF_CORE_I_DQS_TOP→ JWRPNTR1_IOLOGIC_CORE_I_GEARING_PIC_TOP_B
DQSG:JWRPNTR2_DQSBUF_CORE_I_DQS_TOP→ JWRPNTR2_IOLOGIC_CORE_I_GEARING_PIC_TOP_A
DQSG:JWRPNTR2_DQSBUF_CORE_I_DQS_TOP→ JWRPNTR2_IOLOGIC_CORE_I_GEARING_PIC_TOP_B
N1:JCIBMUXOUTD2→ N1:JBYPASS_DLLDEL_CORE_I0
JINCK_IOLOGIC_CORE_I_GEARING_PIC_TOP_A→ N1:JCLKIN_DLLDEL_CORE_I0
JPADDI_DIFFIO18_CORE_IOA→ N1:JCLKIN_DLLDEL_CORE_I0
N1:JZ_I4_0→ N1:JCODE0_DLLDEL_CORE_I0
N1:JZ_I4_1→ N1:JCODE1_DLLDEL_CORE_I0
N1:JZ_I4_2→ N1:JCODE2_DLLDEL_CORE_I0
N1:JZ_I4_3→ N1:JCODE3_DLLDEL_CORE_I0
N1:JZ_I4_4→ N1:JCODE4_DLLDEL_CORE_I0
N1:JZ_I4_5→ N1:JCODE5_DLLDEL_CORE_I0
N1:JZ_I4_6→ N1:JCODE6_DLLDEL_CORE_I0
N1:JZ_I4_7→ N1:JCODE7_DLLDEL_CORE_I0
N1:JZ_I4_8→ N1:JCODE8_DLLDEL_CORE_I0
N1:JCIBMUXOUTD7→ N1:JDIR_DLLDEL_CORE_I0
JRXDATA0_IOLOGIC_CORE_I_GEARING_PIC_TOP_A→ N1:JF0
JRXDATA1_IOLOGIC_CORE_I_GEARING_PIC_TOP_A→ N1:JF1
JRXDATA2_IOLOGIC_CORE_I_GEARING_PIC_TOP_A→ N1:JF2
JRXDATA3_IOLOGIC_CORE_I_GEARING_PIC_TOP_A→ N1:JF3
JRXDATA4_IOLOGIC_CORE_I_GEARING_PIC_TOP_A→ N1:JF4
JRXDATA5_IOLOGIC_CORE_I_GEARING_PIC_TOP_A→ N1:JF5
JRXDATA6_IOLOGIC_CORE_I_GEARING_PIC_TOP_A→ N1:JF6
JRXDATA7_IOLOGIC_CORE_I_GEARING_PIC_TOP_A→ N1:JF7
N1:JCIBMUXOUTD1→ N1:JLOAD_N_DLLDEL_CORE_I0
N1:JCIBMUXOUTC7→ N1:JMOVE_DLLDEL_CORE_I0
JINFF_IOLOGIC_CORE_I_GEARING_PIC_TOP_A→ N1:JQ0
JINDD_IOLOGIC_CORE_I_GEARING_PIC_TOP_A→ N1:JQ1
JINLP_DIFFIO18_CORE_IOA→ N1:JQ1
JPADDI_DIFFIO18_CORE_IOA→ N1:JQ1
JEDETERR_IOLOGIC_CORE_I_GEARING_PIC_TOP_A→ N1:JQ2
JCOUT_IOLOGIC_CORE_I_GEARING_PIC_TOP_A→ N1:JQ3
JRXDATA8_IOLOGIC_CORE_I_GEARING_PIC_TOP_A→ N1:JQ4
JRXDATA9_IOLOGIC_CORE_I_GEARING_PIC_TOP_A→ N1:JQ5
N1:JCOUT_DLLDEL_CORE_I0→ N1:JQ6
JRXDATA0_IOLOGIC_CORE_I_GEARING_PIC_TOP_B→ N1E1:JF0
JRXDATA1_IOLOGIC_CORE_I_GEARING_PIC_TOP_B→ N1E1:JF1
JRXDATA2_IOLOGIC_CORE_I_GEARING_PIC_TOP_B→ N1E1:JF2
JRXDATA3_IOLOGIC_CORE_I_GEARING_PIC_TOP_B→ N1E1:JF3
JRXDATA4_IOLOGIC_CORE_I_GEARING_PIC_TOP_B→ N1E1:JF4
JRXDATA5_IOLOGIC_CORE_I_GEARING_PIC_TOP_B→ N1E1:JF5
JRXDATA6_IOLOGIC_CORE_I_GEARING_PIC_TOP_B→ N1E1:JF6
JRXDATA7_IOLOGIC_CORE_I_GEARING_PIC_TOP_B→ N1E1:JF7
JINFF_IOLOGIC_CORE_I_GEARING_PIC_TOP_B→ N1E1:JQ0
JINDD_IOLOGIC_CORE_I_GEARING_PIC_TOP_B→ N1E1:JQ1
JINLP_SEIO18_CORE_IOB→ N1E1:JQ1
JPADDI_SEIO18_CORE_IOB→ N1E1:JQ1
JEDETERR_IOLOGIC_CORE_I_GEARING_PIC_TOP_B→ N1E1:JQ2
JCOUT_IOLOGIC_CORE_I_GEARING_PIC_TOP_B→ N1E1:JQ3
JRXDATA8_IOLOGIC_CORE_I_GEARING_PIC_TOP_B→ N1E1:JQ4
JRXDATA9_IOLOGIC_CORE_I_GEARING_PIC_TOP_B→ N1E1:JQ5