SYSIO_B2_0_EVEN Tile Documentation

Tile Bels

NameType
PIOA SEIO33_CORE
PIOB SEIO33_CORE

Config Bitmap

 
 
 
 
 
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Configuration Enums

Configuration enum PIOA.BASE_TYPE

Value F0B8 F0B10 F1B8 F2B7 F2B8 F3B9 F3B10 F3B11 F4B9 F5B9 F5B10 F6B9 F7B10 F9B10 F10B6 F11B11 F12B11 F14B11 F15B9
BIDIR_LVCMOS12 - 1 - - - - 1 1 - 1 - 1 - - - - - 1 -
BIDIR_LVCMOS15 - 1 - - - - 1 1 - 1 1 1 1 - - - - - -
BIDIR_LVCMOS18 - 1 - - - - 1 1 - 1 1 1 - - - - - - -
BIDIR_LVCMOS25 - 1 - - - - 1 - - 1 - 1 - - - - 1 - -
BIDIR_LVCMOS33 - 1 - - - - 1 - - 1 - 1 - - - - - - -
INPUT_LVCMOS10 - 1 - - - - 1 1 - 1 - 1 - - - 1 - 1 -
INPUT_LVCMOS12 - - - - - - - 1 1 - - - - - - - - 1 -
INPUT_LVCMOS15 - - - - - - - 1 1 - 1 - 1 - - - - - -
INPUT_LVCMOS18 - - - - - - - 1 1 - 1 - - - - - - - -
INPUT_LVCMOS25 - - - - - - - - 1 - - - - - - - 1 - -
INPUT_LVCMOS33 - - - - - - - - 1 - - - - - - - - - -
NONE - 1 - - - - - - - - - - - - - - - - -
OUTPUT_LVCMOS12 - 1 - - - 1 1 1 1 1 - 1 - 1 - - - - -
OUTPUT_LVCMOS15 - 1 - - - 1 1 1 1 1 - 1 - 1 - - - - -
OUTPUT_LVCMOS18 - 1 - - - 1 1 1 1 1 - 1 - 1 - - - - -
OUTPUT_LVCMOS25 - 1 - - - 1 1 1 1 1 - 1 - 1 - - - - -
OUTPUT_LVCMOS25D 1 1 1 1 1 1 1 1 1 1 - 1 - 1 1 - - - 1
OUTPUT_LVCMOS33 - 1 - - - 1 1 1 1 1 - 1 - 1 - - - - -
OUTPUT_LVCMOS33D 1 1 1 1 1 1 1 1 1 1 - 1 - 1 1 - - - 1

Configuration enum PIOA.CLAMP

Value F2B9
OFF 0
ON 1

Configuration enum PIOA.DFTDO2DI

Value F15B11
DISABLED -
ENABLED 1

Configuration enum PIOA.DRIVE_1V2

Value F0B10 F1B10 F2B10 F3B10 F4B10
12 1 0 1 1 1
2 0 0 1 0 1
4 0 1 0 1 0
8 1 0 0 1 0

Configuration enum PIOA.DRIVE_1V5

Value F0B10 F1B10 F2B10 F3B10 F4B10
12 1 0 1 1 1
2 0 0 1 0 1
4 0 1 0 1 0
8 1 0 0 1 0

Configuration enum PIOA.DRIVE_1V8

Value F0B10 F1B10 F2B10 F3B10 F4B10
2 0 0 1 0 1
4 0 1 0 1 0
50RS 1 0 0 1 0
8 1 0 0 1 0

Configuration enum PIOA.DRIVE_2V5

Value F0B10 F1B10 F2B10 F3B10 F4B10
10 1 1 0 0 0
2 0 0 1 0 1
4 0 1 0 1 0
50RS 1 0 0 1 0
8 1 0 0 1 0

Configuration enum PIOA.DRIVE_3V3

Value F0B10 F1B10 F2B10 F3B10 F4B10
12 1 0 1 1 1
2 0 0 1 0 1
4 0 1 0 1 0
50RS 0 0 0 0 1
8 1 0 0 1 0

Configuration enum PIOA.GLITCHFILTER

Value F10B10
OFF 1
ON -

Configuration enum PIOA.HYSTERESIS_1V5

Value F3B11 F5B10 F7B10
OFF 0 0 0
ON 1 1 1

Configuration enum PIOA.HYSTERESIS_1V8

Value F3B11 F5B10
OFF 0 0
ON 1 1

Configuration enum PIOA.HYSTERESIS_2V5

Value F12B11
OFF 0
ON 1

Configuration enum PIOA.LOOPBKCD2AB

Value F0B9
DISABLED -
ENABLED 1

Configuration enum PIOA.OPENDRAIN

Value F10B11
OFF -
ON 1

Configuration enum PIOA.PULLMODE

Value F6B10 F8B10 F9B10
DOWN 0 0 0
I3C 1 1 1
KEEPER 0 1 0
NONE 0 0 1
UP 0 1 1

Configuration enum PIOA.SLEEPHIGHLEAKAGE

Value F7B9
DISABLED -
ENABLED 1

Configuration enum PIOA.SLEWRATE

Value F11B10 F12B10 F13B10 F14B10
FAST 1 1 1 1
MED 1 - - -
SLOW - - - -

Configuration enum PIOA.TERMINATION_1V2

Value F6B11 F7B11 F8B11 F9B11
40 - - - 1
50 - 1 1 -
60 - - 1 -
75 1 1 - -
OFF - - - -

Configuration enum PIOA.TERMINATION_1V5

Value F5B11 F6B11 F7B11 F8B11 F9B11
40 - 1 - - 1
50 1 - 1 1 -
60 - - - 1 -
75 - 1 1 - -
OFF - - - - -

Configuration enum PIOA.TERMINATION_1V8

Value F5B11 F6B11 F7B11 F8B11 F9B11
150 - - 1 - -
40 - - 1 - 1
50 - 1 1 1 -
60 - 1 - 1 -
75 1 1 1 - -
OFF - - - - -

Configuration enum PIOA.TMUX

Value F3B9
INV 1
T -

Configuration enum PIOA.UNDERDRIVE_1V8

Value F7B10
OFF 0
ON 1

Configuration enum PIOA.UNDERDRIVE_3V3

Value F12B11 F13B11
OFF 0 0
ON 1 1

Configuration enum PIOB.BASE_TYPE

Value F0B7 F0B8 F1B8 F2B7 F2B8 F4B11 F5B7 F7B7 F9B7 F10B6 F10B7 F12B8 F14B8 F15B9
BIDIR_LVCMOS12 - 1 - 1 - 1 1 1 - - - - - 1
BIDIR_LVCMOS15 1 1 - 1 - 1 1 - - - - - 1 1
BIDIR_LVCMOS18 1 1 - 1 - 1 1 - - - - - - 1
BIDIR_LVCMOS25 - 1 - 1 - - 1 - 1 - - - - 1
BIDIR_LVCMOS33 - 1 - 1 - - 1 - - - - - - 1
INPUT_LVCMOS10 - 1 - 1 - 1 1 1 - - 1 - - 1
INPUT_LVCMOS12 - - 1 - - 1 - 1 - - - - - -
INPUT_LVCMOS15 1 - 1 - - 1 - - - - - - 1 -
INPUT_LVCMOS18 1 - 1 - - 1 - - - - - - - -
INPUT_LVCMOS25 - - 1 - - - - - 1 - - - - -
INPUT_LVCMOS33 - - 1 - - - - - - - - - - -
NONE - - - - - - 1 - - - - - - -
OUTPUT_LVCMOS12 - 1 1 1 1 1 1 - - - - 1 - 1
OUTPUT_LVCMOS15 - 1 1 1 1 1 1 - - - - 1 - 1
OUTPUT_LVCMOS18 - 1 1 1 1 1 1 - - - - 1 - 1
OUTPUT_LVCMOS25 - 1 1 1 1 1 1 - - - - 1 - 1
OUTPUT_LVCMOS25D - 1 1 1 1 1 1 - - 1 - 1 - 1
OUTPUT_LVCMOS33 - 1 1 1 1 1 1 - - - - 1 - 1
OUTPUT_LVCMOS33D - 1 1 1 1 1 1 - - 1 - 1 - 1

Configuration enum PIOB.CLAMP

Value F3B8
OFF 0
ON 1

Configuration enum PIOB.DFTDO2DI

Value F6B7
DISABLED -
ENABLED 1

Configuration enum PIOB.DRIVE_1V2

Value F1B7 F2B7 F3B7 F4B7 F5B7
12 1 1 1 0 1
2 1 0 1 0 0
4 0 1 0 1 0
8 0 1 0 0 1

Configuration enum PIOB.DRIVE_1V5

Value F1B7 F2B7 F3B7 F4B7 F5B7
12 1 1 1 0 1
2 1 0 1 0 0
4 0 1 0 1 0
8 0 1 0 0 1

Configuration enum PIOB.DRIVE_1V8

Value F1B7 F2B7 F3B7 F4B7 F5B7
2 1 0 1 0 0
4 0 1 0 1 0
50RS 0 1 0 0 1
8 0 1 0 0 1

Configuration enum PIOB.DRIVE_2V5

Value F1B7 F2B7 F3B7 F4B7 F5B7
10 0 0 0 1 1
2 1 0 1 0 0
4 0 1 0 1 0
50RS 0 1 0 0 1
8 0 1 0 0 1

Configuration enum PIOB.DRIVE_3V3

Value F1B7 F2B7 F3B7 F4B7 F5B7
12 1 1 1 0 1
2 1 0 1 0 0
4 0 1 0 1 0
50RS 1 0 0 0 0
8 0 1 0 0 1

Configuration enum PIOB.GLITCHFILTER

Value F11B8
OFF 1
ON -

Configuration enum PIOB.HYSTERESIS_1V5

Value F0B7 F4B11 F14B8
OFF 0 0 0
ON 1 1 1

Configuration enum PIOB.HYSTERESIS_1V8

Value F0B7 F4B11
OFF 0 0
ON 1 1

Configuration enum PIOB.HYSTERESIS_2V5

Value F9B7
OFF 0
ON 1

Configuration enum PIOB.LOOPBKCD2AB

Value F5B8
DISABLED -
ENABLED 1

Configuration enum PIOB.OPENDRAIN

Value F11B7
OFF -
ON 1

Configuration enum PIOB.PULLMODE

Value F12B8 F13B8 F15B8
DOWN 0 0 0
I3C 1 1 1
KEEPER 0 1 0
NONE 1 0 0
UP 1 1 0

Configuration enum PIOB.SLEEPHIGHLEAKAGE

Value F14B9
DISABLED -
ENABLED 1

Configuration enum PIOB.SLEWRATE

Value F7B8 F8B8 F9B8 F10B8
FAST 1 1 1 1
MED - - - 1
SLOW - - - -

Configuration enum PIOB.TERMINATION_1V2

Value F12B7 F13B7 F14B7 F15B7
40 1 - - -
50 - 1 1 -
60 - 1 - -
75 - - 1 1
OFF - - - -

Configuration enum PIOB.TERMINATION_1V5

Value F0B6 F12B7 F13B7 F14B7 F15B7
40 - 1 - - 1
50 1 - 1 1 -
60 - - 1 - -
75 - - - 1 1
OFF - - - - -

Configuration enum PIOB.TERMINATION_1V8

Value F0B6 F12B7 F13B7 F14B7 F15B7
150 - - - 1 -
40 - 1 - 1 -
50 - - 1 1 1
60 - - 1 - 1
75 1 - - 1 1
OFF - - - - -

Configuration enum PIOB.TMUX

Value F2B8
INV 1
T -

Configuration enum PIOB.UNDERDRIVE_1V8

Value F8B7 F14B8
OFF 0 0
ON 1 1

Configuration enum PIOB.UNDERDRIVE_3V3

Value F8B7 F9B7
OFF 0 0
ON 1 1

Configuration enum SIOLOGICA.CEINMUX

Value F0B1 F15B2
1 - 1
CEIN 1 -
INV - -

Configuration enum SIOLOGICA.CEOUTMUX

Value F1B1 F14B2
1 - 1
CEOUT 1 -
INV - -

Configuration enum SIOLOGICA.GSR

Value F5B2
DISABLED 1
ENABLED -

Configuration enum SIOLOGICA.IDDRX1_ODDRX1.OUTPUT

Value F11B3
DISABLED -
ENABLED 1

Configuration enum SIOLOGICA.INMUX

Value F12B2
BYPASS -
DELAY 1

Configuration enum SIOLOGICA.INREG.REGSET

Value F4B2
RESET -
SET 1

Configuration enum SIOLOGICA.IREG_OREG.OUTPUT

Value F12B3
DISABLED -
ENABLED 1

Configuration enum SIOLOGICA.LSRINMUX

Value F8B2 F10B2
0 - -
INV 1 -
LSRIN 1 1

Configuration enum SIOLOGICA.LSROUTMUX

Value F9B2 F14B1
0 - -
INV - 1
LSROUT 1 1

Configuration enum SIOLOGICA.MODE

Value F2B3
IDDRX1_ODDRX1 1
IREG_OREG -
NONE -

Configuration enum SIOLOGICA.OUTMUX

Value F3B2
BYPASS -
DELAY 1

Configuration enum SIOLOGICA.OUTREG.REGSET

Value F8B1
RESET -
SET 1

Configuration enum SIOLOGICA.SCLKINMUX

Value F14B3 F15B3
0 - -
INV 1 1
SCLKIN 1 -

Configuration enum SIOLOGICA.SCLKOUTMUX

Value F0B3 F1B3
0 - -
INV 1 1
SCLKOUT - 1

Configuration enum SIOLOGICA.SRMODE

Value F6B2
ASYNC -
LSR_OVER_CE 1

Configuration enum SIOLOGICA.TSREG.REGSET

Value F9B1
RESET -
SET 1

Configuration enum SIOLOGICB.CEINMUX

Value F0B4 F1B4
1 1 -
CEIN - 1
INV - -

Configuration enum SIOLOGICB.CEOUTMUX

Value F2B4 F15B5
1 - 1
CEOUT 1 -
INV - -

Configuration enum SIOLOGICB.GSR

Value F2B6
DISABLED 1
ENABLED -

Configuration enum SIOLOGICB.IDDRX1_ODDRX1.OUTPUT

Value F7B0
DISABLED -
ENABLED 1

Configuration enum SIOLOGICB.INMUX

Value F13B5
BYPASS -
DELAY 1

Configuration enum SIOLOGICB.INREG.REGSET

Value F11B6
RESET -
SET 1

Configuration enum SIOLOGICB.IREG_OREG.OUTPUT

Value F8B0
DISABLED -
ENABLED 1

Configuration enum SIOLOGICB.LSRINMUX

Value F9B5 F11B5
0 - -
INV 1 -
LSRIN 1 1

Configuration enum SIOLOGICB.LSROUTMUX

Value F5B6 F10B5
0 - -
INV 1 -
LSROUT 1 1

Configuration enum SIOLOGICB.MODE

Value F12B6
IDDRX1_ODDRX1 1
IREG_OREG -
NONE -

Configuration enum SIOLOGICB.OUTMUX

Value F9B6
BYPASS -
DELAY 1

Configuration enum SIOLOGICB.OUTREG.REGSET

Value F9B4
RESET -
SET 1

Configuration enum SIOLOGICB.SCLKINMUX

Value F10B0 F11B0
0 - -
INV 1 1
SCLKIN 1 -

Configuration enum SIOLOGICB.SCLKOUTMUX

Value F5B0 F6B0
0 - -
INV 1 1
SCLKOUT - 1

Configuration enum SIOLOGICB.SRMODE

Value F3B6
ASYNC -
LSR_OVER_CE 1

Configuration enum SIOLOGICB.TSREG.REGSET

Value F10B4
RESET -
SET 1

Fixed Connections

SourceSink
W1:JCE0→ JCEIN_SIOLOGIC_CORE_IBASE_PIC_A
W1:JCE1→ JCEIN_SIOLOGIC_CORE_IBASE_PIC_B
W1:JCE0→ JCEOUT_SIOLOGIC_CORE_IBASE_PIC_A
W1:JCE1→ JCEOUT_SIOLOGIC_CORE_IBASE_PIC_B
JPADDI_SEIO33_CORE_IOA→ JDI_SIOLOGIC_CORE_IBASE_PIC_A
JPADDI_SEIO33_CORE_IOB→ JDI_SIOLOGIC_CORE_IBASE_PIC_B
JTXDATA0_SIOLOGIC_CORE_IBASE_PIC_A→ JDOUT_SIOLOGIC_CORE_IBASE_PIC_A
JTXDATA0_SIOLOGIC_CORE_IBASE_PIC_B→ JDOUT_SIOLOGIC_CORE_IBASE_PIC_B
W1:JCIBMUXOUTA2→ JI3CRESEN_SEIO33_CORE_IOA
W1:JCIBMUXOUTA5→ JI3CRESEN_SEIO33_CORE_IOB
W1:JCIBMUXOUTB2→ JI3CWKPU_SEIO33_CORE_IOA
W1:JCIBMUXOUTB5→ JI3CWKPU_SEIO33_CORE_IOB
JDI_SIOLOGIC_CORE_IBASE_PIC_A→ JINDD_SIOLOGIC_CORE_IBASE_PIC_A
JDI_SIOLOGIC_CORE_IBASE_PIC_B→ JINDD_SIOLOGIC_CORE_IBASE_PIC_B
W1:JLSR0→ JLSRIN_SIOLOGIC_CORE_IBASE_PIC_A
W1:JLSR1→ JLSRIN_SIOLOGIC_CORE_IBASE_PIC_B
W1:JLSR0→ JLSROUT_SIOLOGIC_CORE_IBASE_PIC_A
W1:JLSR1→ JLSROUT_SIOLOGIC_CORE_IBASE_PIC_B
W1:JCIBMUXOUTA0→ JPADDO_SEIO33_CORE_IOA
JDOUT_SIOLOGIC_CORE_IBASE_PIC_A→ JPADDO_SEIO33_CORE_IOA
W1:JCIBMUXOUTC0→ JPADDO_SEIO33_CORE_IOB
JDOUT_SIOLOGIC_CORE_IBASE_PIC_B→ JPADDO_SEIO33_CORE_IOB
W1:JCIBMUXOUTB1→ JPADDT_SEIO33_CORE_IOA
JTOUT_SIOLOGIC_CORE_IBASE_PIC_A→ JPADDT_SEIO33_CORE_IOA
W1:JCIBMUXOUTB4→ JPADDT_SEIO33_CORE_IOB
JTOUT_SIOLOGIC_CORE_IBASE_PIC_B→ JPADDT_SEIO33_CORE_IOB
W1:JCLK0→ JSCLKIN_SIOLOGIC_CORE_IBASE_PIC_A
W1:JCLK1→ JSCLKIN_SIOLOGIC_CORE_IBASE_PIC_B
W1:JCLK0→ JSCLKOUT_SIOLOGIC_CORE_IBASE_PIC_A
W1:JCLK1→ JSCLKOUT_SIOLOGIC_CORE_IBASE_PIC_B
JTSDATA0_SIOLOGIC_CORE_IBASE_PIC_A→ JTOUT_SIOLOGIC_CORE_IBASE_PIC_A
JTSDATA0_SIOLOGIC_CORE_IBASE_PIC_B→ JTOUT_SIOLOGIC_CORE_IBASE_PIC_B
W1:JCIBMUXOUTB1→ JTSDATA0_SIOLOGIC_CORE_IBASE_PIC_A
W1:JCIBMUXOUTB4→ JTSDATA0_SIOLOGIC_CORE_IBASE_PIC_B
W1:JCIBMUXOUTA0→ JTXDATA0_SIOLOGIC_CORE_IBASE_PIC_A
W1:JCIBMUXOUTC0→ JTXDATA0_SIOLOGIC_CORE_IBASE_PIC_B
W1:JCIBMUXOUTB0→ JTXDATA1_SIOLOGIC_CORE_IBASE_PIC_A
W1:JCIBMUXOUTD0→ JTXDATA1_SIOLOGIC_CORE_IBASE_PIC_B
JRXDATA0_SIOLOGIC_CORE_IBASE_PIC_A→ W1:JF0
JRXDATA1_SIOLOGIC_CORE_IBASE_PIC_A→ W1:JF1
JINFF_SIOLOGIC_CORE_IBASE_PIC_A→ W1:JF4
JINDD_SIOLOGIC_CORE_IBASE_PIC_A→ W1:JF5
JPADDI_SEIO33_CORE_IOA→ W1:JF5
JRXDATA0_SIOLOGIC_CORE_IBASE_PIC_B→ W1:JQ0
JRXDATA1_SIOLOGIC_CORE_IBASE_PIC_B→ W1:JQ1
JINFF_SIOLOGIC_CORE_IBASE_PIC_B→ W1:JQ4
JINDD_SIOLOGIC_CORE_IBASE_PIC_B→ W1:JQ5
JPADDI_SEIO33_CORE_IOB→ W1:JQ5