SYSIO_B0_0_15K Tile Documentation

Tile Bels

NameType
PIOA SEIO33_CORE
PIOB SEIO33_CORE
SIOLOGICA SIOLOGIC
SIOLOGICB SIOLOGIC

Config Bitmap

 
 
 
 
 
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Configuration Enums

Configuration enum PIOA.BASE_TYPE

Value F11B0 F12B0 F14B0 F18B0 F21B0 F23B0 F25B0 F27B0 F36B0 F37B0 F38B0 F39B0 F44B0 F50B0 F51B0 F52B0 F53B0 F67B0 F105B0
BIDIR_LVCMOS12 - - 1 1 1 - - - - - 1 1 1 - - - - - -
BIDIR_LVCMOS15 - - - 1 1 1 1 - - - 1 1 1 - - - - - -
BIDIR_LVCMOS18 - - - 1 1 1 - - - - 1 1 1 - - - - - -
BIDIR_LVCMOS25 - 1 - 1 1 - - - - - 1 1 - - - - - - -
BIDIR_LVCMOS33 - - - 1 1 - - - - - 1 1 - - - - - - -
INPUT_LVCMOS10 1 - 1 1 1 - - - - - 1 1 1 - - - - - -
INPUT_LVCMOS12 - - 1 - - - - - - 1 - - 1 - - - - - -
INPUT_LVCMOS15 - - - - - 1 1 - - 1 - - 1 - - - - - -
INPUT_LVCMOS18 - - - - - 1 - - - 1 - - 1 - - - - - -
INPUT_LVCMOS25 - 1 - - - - - - - 1 - - - - - - - - -
INPUT_LVCMOS33 - - - - - - - - - 1 - - - - - - - - -
NONE - - - 1 - - - - - - - - - - - - - - -
OUTPUT_LVCMOS12 - - - 1 1 - - 1 1 1 1 1 1 - - - - - -
OUTPUT_LVCMOS15 - - - 1 1 - - 1 1 1 1 1 1 - - - - - -
OUTPUT_LVCMOS18 - - - 1 1 - - 1 1 1 1 1 1 - - - - - -
OUTPUT_LVCMOS25 - - - 1 1 - - 1 1 1 1 1 1 - - - - - -
OUTPUT_LVCMOS25D - - - 1 1 - - 1 1 1 1 1 1 1 1 1 1 1 1
OUTPUT_LVCMOS33 - - - 1 1 - - 1 1 1 1 1 1 - - - - - -
OUTPUT_LVCMOS33D - - - 1 1 - - 1 1 1 1 1 1 1 1 1 1 1 1

Configuration enum PIOA.CLAMP

Value F35B0
OFF 0
ON 1

Configuration enum PIOA.DFTDO2DI

Value F16B0
DISABLED -
ENABLED 1

Configuration enum PIOA.DRIVE_1V2

Value F18B0 F19B0 F20B0 F21B0 F22B0
12 1 0 1 1 1
2 0 0 1 0 1
4 0 1 0 1 0
8 1 0 0 1 0

Configuration enum PIOA.DRIVE_1V5

Value F18B0 F19B0 F20B0 F21B0 F22B0
12 1 0 1 1 1
2 0 0 1 0 1
4 0 1 0 1 0
8 1 0 0 1 0

Configuration enum PIOA.DRIVE_1V8

Value F18B0 F19B0 F20B0 F21B0 F22B0
2 0 0 1 0 1
4 0 1 0 1 0
50RS 1 0 0 1 0
8 1 0 0 1 0

Configuration enum PIOA.DRIVE_2V5

Value F18B0 F19B0 F20B0 F21B0 F22B0
10 1 1 0 0 0
2 0 0 1 0 1
4 0 1 0 1 0
50RS 1 0 0 1 0
8 1 0 0 1 0

Configuration enum PIOA.DRIVE_3V3

Value F18B0 F19B0 F20B0 F21B0 F22B0
12 1 0 1 1 1
2 0 0 1 0 1
4 0 1 0 1 0
50RS 0 0 0 0 1
8 1 0 0 1 0

Configuration enum PIOA.GLITCHFILTER

Value F28B0
OFF 1
ON -

Configuration enum PIOA.HYSTERESIS_1V5

Value F23B0 F25B0 F44B0
OFF 0 0 0
ON 1 1 1

Configuration enum PIOA.HYSTERESIS_1V8

Value F23B0 F44B0
OFF 0 0
ON 1 1

Configuration enum PIOA.HYSTERESIS_2V5

Value F12B0
OFF 0
ON 1

Configuration enum PIOA.LOOPBKCD2AB

Value F33B0
DISABLED -
ENABLED 1

Configuration enum PIOA.OPENDRAIN

Value F10B0
OFF -
ON 1

Configuration enum PIOA.PULLMODE

Value F24B0 F26B0 F27B0
DOWN 0 0 0
I3C 1 1 1
KEEPER 0 1 0
NONE 0 0 1
UP 0 1 1

Configuration enum PIOA.SLEEPHIGHLEAKAGE

Value F40B0
DISABLED -
ENABLED 1

Configuration enum PIOA.SLEWRATE

Value F29B0 F30B0 F31B0 F32B0
FAST 1 1 1 1
MED 1 - - -
SLOW - - - -

Configuration enum PIOA.TERMINATION_1V2

Value F6B0 F7B0 F8B0 F9B0
40 - - - 1
50 - 1 1 -
60 - - 1 -
75 1 1 - -
OFF - - - -

Configuration enum PIOA.TERMINATION_1V5

Value F5B0 F6B0 F7B0 F8B0 F9B0
40 - 1 - - 1
50 1 - 1 1 -
60 - - - 1 -
75 - 1 1 - -
OFF - - - - -

Configuration enum PIOA.TERMINATION_1V8

Value F5B0 F6B0 F7B0 F8B0 F9B0
150 - - 1 - -
40 - - 1 - 1
50 - 1 1 1 -
60 - 1 - 1 -
75 1 1 1 - -
OFF - - - - -

Configuration enum PIOA.TMUX

Value F36B0
INV 1
T -

Configuration enum PIOA.UNDERDRIVE_1V8

Value F25B0
OFF 0
ON 1

Configuration enum PIOA.UNDERDRIVE_3V3

Value F12B0 F13B0
OFF 0 0
ON 1 1

Configuration enum PIOB.BASE_TYPE

Value F45B0 F50B0 F51B0 F52B0 F53B0 F61B0 F63B0 F65B0 F67B0 F71B0 F77B0 F78B0 F79B0 F105B0
BIDIR_LVCMOS12 1 1 1 - - - - - 1 1 1 - - -
BIDIR_LVCMOS15 1 1 1 - - - 1 1 1 1 - - - -
BIDIR_LVCMOS18 1 1 1 - - - - 1 1 1 - - - -
BIDIR_LVCMOS25 - 1 1 - - - - - 1 1 - 1 - -
BIDIR_LVCMOS33 - 1 1 - - - - - 1 1 - - - -
INPUT_LVCMOS10 1 1 1 - - - - - 1 1 1 - 1 -
INPUT_LVCMOS12 1 - - 1 - - - - - - 1 - - -
INPUT_LVCMOS15 1 - - 1 - - 1 1 - - - - - -
INPUT_LVCMOS18 1 - - 1 - - - 1 - - - - - -
INPUT_LVCMOS25 - - - 1 - - - - - - - 1 - -
INPUT_LVCMOS33 - - - 1 - - - - - - - - - -
NONE - - - - - - - - - 1 - - - -
OUTPUT_LVCMOS12 1 1 1 1 1 1 - - 1 1 - - - -
OUTPUT_LVCMOS15 1 1 1 1 1 1 - - 1 1 - - - -
OUTPUT_LVCMOS18 1 1 1 1 1 1 - - 1 1 - - - -
OUTPUT_LVCMOS25 1 1 1 1 1 1 - - 1 1 - - - -
OUTPUT_LVCMOS25D 1 1 1 1 1 1 - - 1 1 - - - 1
OUTPUT_LVCMOS33 1 1 1 1 1 1 - - 1 1 - - - -
OUTPUT_LVCMOS33D 1 1 1 1 1 1 - - 1 1 - - - 1

Configuration enum PIOB.CLAMP

Value F54B0
OFF 0
ON 1

Configuration enum PIOB.DFTDO2DI

Value F75B0
DISABLED -
ENABLED 1

Configuration enum PIOB.DRIVE_1V2

Value F66B0 F67B0 F68B0 F70B0 F71B0
12 1 1 1 0 1
2 1 0 1 0 0
4 0 1 0 1 0
8 0 1 0 0 1

Configuration enum PIOB.DRIVE_1V5

Value F66B0 F67B0 F68B0 F70B0 F71B0
12 1 1 1 0 1
2 1 0 1 0 0
4 0 1 0 1 0
8 0 1 0 0 1

Configuration enum PIOB.DRIVE_1V8

Value F66B0 F67B0 F68B0 F70B0 F71B0
2 1 0 1 0 0
4 0 1 0 1 0
50RS 0 1 0 0 1
8 0 1 0 0 1

Configuration enum PIOB.DRIVE_2V5

Value F66B0 F67B0 F68B0 F70B0 F71B0
10 0 0 0 1 1
2 1 0 1 0 0
4 0 1 0 1 0
50RS 0 1 0 0 1
8 0 1 0 0 1

Configuration enum PIOB.DRIVE_3V3

Value F66B0 F67B0 F68B0 F70B0 F71B0
12 1 1 1 0 1
2 1 0 1 0 0
4 0 1 0 1 0
50RS 1 0 0 0 0
8 0 1 0 0 1

Configuration enum PIOB.GLITCHFILTER

Value F60B0
OFF 1
ON -

Configuration enum PIOB.HYSTERESIS_1V5

Value F45B0 F63B0 F65B0
OFF 0 0 0
ON 1 1 1

Configuration enum PIOB.HYSTERESIS_1V8

Value F45B0 F65B0
OFF 0 0
ON 1 1

Configuration enum PIOB.HYSTERESIS_2V5

Value F78B0
OFF 0
ON 1

Configuration enum PIOB.LOOPBKCD2AB

Value F55B0
DISABLED -
ENABLED 1

Configuration enum PIOB.OPENDRAIN

Value F80B0
OFF -
ON 1

Configuration enum PIOB.PULLMODE

Value F61B0 F62B0 F64B0
DOWN 0 0 0
I3C 1 1 1
KEEPER 0 1 0
NONE 1 0 0
UP 1 1 0

Configuration enum PIOB.SLEEPHIGHLEAKAGE

Value F49B0
DISABLED -
ENABLED 1

Configuration enum PIOB.SLEWRATE

Value F56B0 F57B0 F58B0 F59B0
FAST 1 1 1 1
MED - - - 1
SLOW - - - -

Configuration enum PIOB.TERMINATION_1V2

Value F82B0 F83B0 F84B0 F101B0
40 1 - - -
50 - 1 1 -
60 - 1 - -
75 - - 1 1
OFF - - - -

Configuration enum PIOB.TERMINATION_1V5

Value F82B0 F83B0 F84B0 F101B0 F102B0
40 1 - - 1 -
50 - 1 1 - 1
60 - 1 - - -
75 - - 1 1 -
OFF - - - - -

Configuration enum PIOB.TERMINATION_1V8

Value F82B0 F83B0 F84B0 F101B0 F102B0
150 - - 1 - -
40 1 - 1 - -
50 - 1 1 1 -
60 - 1 - 1 -
75 - - 1 1 1
OFF - - - - -

Configuration enum PIOB.TMUX

Value F53B0
INV 1
T -

Configuration enum PIOB.UNDERDRIVE_1V8

Value F63B0 F81B0
OFF 0 0
ON 1 1

Configuration enum PIOB.UNDERDRIVE_3V3

Value F78B0 F81B0
OFF 0 0
ON 1 1

Configuration enum SIOLOGICA.CEINMUX

Value F11B1 F12B1
1 - 1
CEIN 1 -
INV - -

Configuration enum SIOLOGICA.CEOUTMUX

Value F10B1 F13B1
1 - 1
CEOUT 1 -
INV - -

Configuration enum SIOLOGICA.GSR

Value F24B1
DISABLED 1
ENABLED -

Configuration enum SIOLOGICA.IDDRX1_ODDRX1.OUTPUT

Value F32B1
DISABLED -
ENABLED 1

Configuration enum SIOLOGICA.IDDRX1_ODDRX1.TRISTATE

Value F22B1
DISABLED -
ENABLED 1

Configuration enum SIOLOGICA.INMUX

Value F40B1
BYPASS -
DELAY 1

Configuration enum SIOLOGICA.INREG.REGSET

Value F41B1
RESET -
SET 1

Configuration enum SIOLOGICA.IREG_OREG.OUTPUT

Value F31B1
DISABLED -
ENABLED 1

Configuration enum SIOLOGICA.IREG_OREG.TRISTATE

Value F22B1
DISABLED -
ENABLED 1

Configuration enum SIOLOGICA.LSRINMUX

Value F15B1 F17B1
0 - -
INV - 1
LSRIN 1 1

Configuration enum SIOLOGICA.LSROUTMUX

Value F16B1 F21B1
0 - -
INV - 1
LSROUT 1 1

Configuration enum SIOLOGICA.MODE

Value F54B1
IDDRX1_ODDRX1 1
IREG_OREG -
NONE -

Configuration enum SIOLOGICA.OUTMUX

Value F43B1
BYPASS -
DELAY 1

Configuration enum SIOLOGICA.OUTREG.REGSET

Value F4B1
RESET -
SET 1

Configuration enum SIOLOGICA.SCLKINMUX

Value F28B1 F29B1
0 - -
INV 1 1
SCLKIN - 1

Configuration enum SIOLOGICA.SCLKOUTMUX

Value F33B1 F34B1
0 - -
INV 1 1
SCLKOUT 1 -

Configuration enum SIOLOGICA.SRMODE

Value F23B1
ASYNC -
LSR_OVER_CE 1

Configuration enum SIOLOGICA.TSREG.REGSET

Value F3B1
RESET -
SET 1

Configuration enum SIOLOGICB.CEINMUX

Value F66B1 F67B1
1 - 1
CEIN 1 -
INV - -

Configuration enum SIOLOGICB.CEOUTMUX

Value F65B1 F68B1
1 - 1
CEOUT 1 -
INV - -

Configuration enum SIOLOGICB.GSR

Value F79B1
DISABLED 1
ENABLED -

Configuration enum SIOLOGICB.IDDRX1_ODDRX1.OUTPUT

Value F89B1
DISABLED -
ENABLED 1

Configuration enum SIOLOGICB.IDDRX1_ODDRX1.TRISTATE

Value F77B1
DISABLED -
ENABLED 1

Configuration enum SIOLOGICB.INMUX

Value F103B0
BYPASS -
DELAY 1

Configuration enum SIOLOGICB.INREG.REGSET

Value F104B0
RESET -
SET 1

Configuration enum SIOLOGICB.IREG_OREG.OUTPUT

Value F88B1
DISABLED -
ENABLED 1

Configuration enum SIOLOGICB.IREG_OREG.TRISTATE

Value F77B1
DISABLED -
ENABLED 1

Configuration enum SIOLOGICB.LSRINMUX

Value F70B1 F72B1
0 - -
INV - 1
LSRIN 1 1

Configuration enum SIOLOGICB.LSROUTMUX

Value F71B1 F76B1
0 - -
INV - 1
LSROUT 1 1

Configuration enum SIOLOGICB.MODE

Value F99B0
IDDRX1_ODDRX1 1
IREG_OREG -
NONE -

Configuration enum SIOLOGICB.OUTMUX

Value F85B0
BYPASS -
DELAY 1

Configuration enum SIOLOGICB.OUTREG.REGSET

Value F59B1
RESET -
SET 1

Configuration enum SIOLOGICB.SCLKINMUX

Value F85B1 F86B1
0 - -
INV 1 1
SCLKIN - 1

Configuration enum SIOLOGICB.SCLKOUTMUX

Value F90B1 F92B1
0 - -
INV 1 1
SCLKOUT 1 -

Configuration enum SIOLOGICB.SRMODE

Value F78B1
ASYNC -
LSR_OVER_CE 1

Configuration enum SIOLOGICB.TSREG.REGSET

Value F58B1
RESET -
SET 1

Fixed Connections

SourceSink
S1:JCE0→ JCEIN_SIOLOGIC_CORE_IBASE_PIC_A
S1:JCE1→ JCEIN_SIOLOGIC_CORE_IBASE_PIC_B
S1:JCE0→ JCEOUT_SIOLOGIC_CORE_IBASE_PIC_A
S1:JCE1→ JCEOUT_SIOLOGIC_CORE_IBASE_PIC_B
JPADDI_SEIO33_CORE_IOA→ JDI_SIOLOGIC_CORE_IBASE_PIC_A
JPADDI_SEIO33_CORE_IOB→ JDI_SIOLOGIC_CORE_IBASE_PIC_B
JTXDATA0_SIOLOGIC_CORE_IBASE_PIC_A→ JDOUT_SIOLOGIC_CORE_IBASE_PIC_A
JTXDATA0_SIOLOGIC_CORE_IBASE_PIC_B→ JDOUT_SIOLOGIC_CORE_IBASE_PIC_B
S1:JCIBMUXOUTA2→ JI3CRESEN_SEIO33_CORE_IOA
S1:JCIBMUXOUTA5→ JI3CRESEN_SEIO33_CORE_IOB
S1:JCIBMUXOUTB2→ JI3CWKPU_SEIO33_CORE_IOA
S1:JCIBMUXOUTB5→ JI3CWKPU_SEIO33_CORE_IOB
JDI_SIOLOGIC_CORE_IBASE_PIC_A→ JINDD_SIOLOGIC_CORE_IBASE_PIC_A
JDI_SIOLOGIC_CORE_IBASE_PIC_B→ JINDD_SIOLOGIC_CORE_IBASE_PIC_B
S1:JLSR0→ JLSRIN_SIOLOGIC_CORE_IBASE_PIC_A
S1:JLSR1→ JLSRIN_SIOLOGIC_CORE_IBASE_PIC_B
S1:JLSR0→ JLSROUT_SIOLOGIC_CORE_IBASE_PIC_A
S1:JLSR1→ JLSROUT_SIOLOGIC_CORE_IBASE_PIC_B
JDOUT_SIOLOGIC_CORE_IBASE_PIC_A→ JPADDO_SEIO33_CORE_IOA
S1:JCIBMUXOUTA0→ JPADDO_SEIO33_CORE_IOA
JDOUT_SIOLOGIC_CORE_IBASE_PIC_B→ JPADDO_SEIO33_CORE_IOB
S1:JCIBMUXOUTC0→ JPADDO_SEIO33_CORE_IOB
JTOUT_SIOLOGIC_CORE_IBASE_PIC_A→ JPADDT_SEIO33_CORE_IOA
S1:JCIBMUXOUTB1→ JPADDT_SEIO33_CORE_IOA
JTOUT_SIOLOGIC_CORE_IBASE_PIC_B→ JPADDT_SEIO33_CORE_IOB
S1:JCIBMUXOUTB4→ JPADDT_SEIO33_CORE_IOB
S1:JCLK0→ JSCLKIN_SIOLOGIC_CORE_IBASE_PIC_A
S1:JCLK1→ JSCLKIN_SIOLOGIC_CORE_IBASE_PIC_B
S1:JCLK0→ JSCLKOUT_SIOLOGIC_CORE_IBASE_PIC_A
S1:JCLK1→ JSCLKOUT_SIOLOGIC_CORE_IBASE_PIC_B
JTSDATA0_SIOLOGIC_CORE_IBASE_PIC_A→ JTOUT_SIOLOGIC_CORE_IBASE_PIC_A
JTSDATA0_SIOLOGIC_CORE_IBASE_PIC_B→ JTOUT_SIOLOGIC_CORE_IBASE_PIC_B
S1:JCIBMUXOUTB1→ JTSDATA0_SIOLOGIC_CORE_IBASE_PIC_A
S1:JCIBMUXOUTB4→ JTSDATA0_SIOLOGIC_CORE_IBASE_PIC_B
S1:JCIBMUXOUTA0→ JTXDATA0_SIOLOGIC_CORE_IBASE_PIC_A
S1:JCIBMUXOUTC0→ JTXDATA0_SIOLOGIC_CORE_IBASE_PIC_B
S1:JCIBMUXOUTB0→ JTXDATA1_SIOLOGIC_CORE_IBASE_PIC_A
S1:JCIBMUXOUTD0→ JTXDATA1_SIOLOGIC_CORE_IBASE_PIC_B
JRXDATA0_SIOLOGIC_CORE_IBASE_PIC_A→ S1:JF0
JRXDATA1_SIOLOGIC_CORE_IBASE_PIC_A→ S1:JF1
JINFF_SIOLOGIC_CORE_IBASE_PIC_A→ S1:JF4
JINDD_SIOLOGIC_CORE_IBASE_PIC_A→ S1:JF5
JPADDI_SEIO33_CORE_IOA→ S1:JF5
JRXDATA0_SIOLOGIC_CORE_IBASE_PIC_B→ S1:JQ0
JRXDATA1_SIOLOGIC_CORE_IBASE_PIC_B→ S1:JQ1
JINFF_SIOLOGIC_CORE_IBASE_PIC_B→ S1:JQ4
JINDD_SIOLOGIC_CORE_IBASE_PIC_B→ S1:JQ5
JPADDI_SEIO33_CORE_IOB→ S1:JQ5