RMID_DLY20 Tile Documentation

Tile Bels

NameType
DCC_R0 DCC
DCC_R1 DCC
DCC_R2 DCC
DCC_R3 DCC
DCC_R4 DCC
DCC_R5 DCC
DCC_R6 DCC
DCC_R7 DCC
DCC_R8 DCC
DCC_R9 DCC
DCC_R10 DCC
DCC_R11 DCC

Config Bitmap

 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
D
D
D
D
D
D
D
D
D
 
 
 
 
 
 
 
R
R
R
R
R
R
R
R
R
R
R
R
R
D
D
D
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
 
 
 
 
 
 
 
 
 
 
 
 
 
R
R
R
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
A
A
A
A
A
A
A
A
A
A
 
 
8

Routing Muxes

Mux driving G:JHPFW0_RMID_CORE_RMIDMUX

Source F9B2 F10B2 F11B2 F12B2
G:JPCLKCIBR4_RMID_CORE_RMIDMUX 0 0 1 0
G:JLRCLKOS3_RMID_CORE_RMIDMUX 0 0 1 1
G:JPCLKCIBR0_RMID_CORE_RMIDMUX 0 1 1 0
G:JLRCLKOS_RMID_CORE_RMIDMUX 0 1 1 1
G:JPCLKT22_RMID_CORE_RMIDMUX 1 0 1 0
G:JPCLKT11_RMID_CORE_RMIDMUX 1 1 1 0

Mux driving G:JHPFW10_RMID_CORE_RMIDMUX

Source F1B4 F2B4 F3B4 F4B4
G:JPCLKCIBR8_RMID_CORE_RMIDMUX 0 0 1 0
G:JLRCLKOS_RMID_CORE_RMIDMUX 0 0 1 1
G:JPCLKCIBR1_RMID_CORE_RMIDMUX 0 1 1 0
G:JLRCLKOP_RMID_CORE_RMIDMUX 0 1 1 1
G:JPCLKT21_RMID_CORE_RMIDMUX 1 0 1 0
G:JPCLKT10_RMID_CORE_RMIDMUX 1 1 1 0

Mux driving G:JHPFW11_RMID_CORE_RMIDMUX

Source F0B4 F13B5 F14B5 F15B5
G:JPCLKCIBR7_RMID_CORE_RMIDMUX 0 0 0 1
G:JPCLKCIBR3_RMID_CORE_RMIDMUX 0 0 1 1
G:JPCLKT21_RMID_CORE_RMIDMUX 0 1 0 1
G:JPCLKT11_RMID_CORE_RMIDMUX 0 1 1 1
G:JLRCLKOS3_RMID_CORE_RMIDMUX 1 0 0 1
G:JLRCLKOS_RMID_CORE_RMIDMUX 1 0 1 1
G:JPCLKCIBR9_RMID_CORE_RMIDMUX 1 1 1 0

Mux driving G:JHPFW1_RMID_CORE_RMIDMUX

Source F5B2 F6B2 F7B2 F8B2
G:JPCLKCIBR5_RMID_CORE_RMIDMUX 0 0 1 0
G:JLRCLKOS4_RMID_CORE_RMIDMUX 0 0 1 1
G:JPCLKCIBR1_RMID_CORE_RMIDMUX 0 1 1 0
G:JLRCLKOP_RMID_CORE_RMIDMUX 0 1 1 1
G:JPCLKT12_RMID_CORE_RMIDMUX 1 0 1 0
G:JPCLKCIBR9_RMID_CORE_RMIDMUX 1 1 0 1
G:JPCLKT10_RMID_CORE_RMIDMUX 1 1 1 0

Mux driving G:JHPFW2_RMID_CORE_RMIDMUX

Source F1B2 F2B2 F3B2 F4B2
G:JPCLKCIBR6_RMID_CORE_RMIDMUX 0 0 1 0
G:JLRCLKOS4_RMID_CORE_RMIDMUX 0 0 1 1
G:JPCLKCIBR2_RMID_CORE_RMIDMUX 0 1 1 0
G:JLRCLKOS_RMID_CORE_RMIDMUX 0 1 1 1
G:JPCLKT20_RMID_CORE_RMIDMUX 1 0 1 0
G:JPCLKCIBR8_RMID_CORE_RMIDMUX 1 1 0 1
G:JPCLKT10_RMID_CORE_RMIDMUX 1 1 1 0

Mux driving G:JHPFW3_RMID_CORE_RMIDMUX

Source F0B2 F13B3 F14B3 F15B3
G:JPCLKCIBR7_RMID_CORE_RMIDMUX 0 0 0 1
G:JPCLKCIBR3_RMID_CORE_RMIDMUX 0 0 1 1
G:JPCLKT21_RMID_CORE_RMIDMUX 0 1 0 1
G:JPCLKT20_RMID_CORE_RMIDMUX 0 1 1 1
G:JLRCLKOS5_RMID_CORE_RMIDMUX 1 0 0 1
G:JLRCLKOS3_RMID_CORE_RMIDMUX 1 0 1 1
G:JPCLKCIBR9_RMID_CORE_RMIDMUX 1 1 1 0

Mux driving G:JHPFW4_RMID_CORE_RMIDMUX

Source F9B3 F10B3 F11B3 F12B3
G:JPCLKCIBR6_RMID_CORE_RMIDMUX 0 0 1 0
G:JLRCLKOS4_RMID_CORE_RMIDMUX 0 0 1 1
G:JPCLKCIBR4_RMID_CORE_RMIDMUX 0 1 1 0
G:JLRCLKOS2_RMID_CORE_RMIDMUX 0 1 1 1
G:JPCLKT22_RMID_CORE_RMIDMUX 1 0 1 0
G:JPCLKCIBR8_RMID_CORE_RMIDMUX 1 1 0 1
G:JPCLKT11_RMID_CORE_RMIDMUX 1 1 1 0

Mux driving G:JHPFW5_RMID_CORE_RMIDMUX

Source F5B3 F6B3 F7B3 F8B3
G:JPCLKCIBR7_RMID_CORE_RMIDMUX 0 0 1 0
G:JLRCLKOS3_RMID_CORE_RMIDMUX 0 0 1 1
G:JPCLKCIBR2_RMID_CORE_RMIDMUX 0 1 1 0
G:JLRCLKOP_RMID_CORE_RMIDMUX 0 1 1 1
G:JPCLKT21_RMID_CORE_RMIDMUX 1 0 1 0
G:JPCLKT10_RMID_CORE_RMIDMUX 1 1 1 0

Mux driving G:JHPFW6_RMID_CORE_RMIDMUX

Source F1B3 F2B3 F3B3 F4B3
G:JPCLKCIBR5_RMID_CORE_RMIDMUX 0 0 1 0
G:JLRCLKOS5_RMID_CORE_RMIDMUX 0 0 1 1
G:JPCLKCIBR3_RMID_CORE_RMIDMUX 0 1 1 0
G:JLRCLKOS2_RMID_CORE_RMIDMUX 0 1 1 1
G:JPCLKT22_RMID_CORE_RMIDMUX 1 0 1 0
G:JPCLKCIBR8_RMID_CORE_RMIDMUX 1 1 0 1
G:JPCLKT20_RMID_CORE_RMIDMUX 1 1 1 0

Mux driving G:JHPFW7_RMID_CORE_RMIDMUX

Source F0B3 F13B4 F14B4 F15B4
G:JPCLKCIBR2_RMID_CORE_RMIDMUX 0 0 0 1
G:JPCLKCIBR0_RMID_CORE_RMIDMUX 0 0 1 1
G:JPCLKT12_RMID_CORE_RMIDMUX 0 1 0 1
G:JPCLKT11_RMID_CORE_RMIDMUX 0 1 1 1
G:JLRCLKOS5_RMID_CORE_RMIDMUX 1 0 0 1
G:JLRCLKOP_RMID_CORE_RMIDMUX 1 0 1 1
G:JPCLKCIBR5_RMID_CORE_RMIDMUX 1 1 1 0

Mux driving G:JHPFW8_RMID_CORE_RMIDMUX

Source F9B4 F10B4 F11B4 F12B4
G:JPCLKCIBR4_RMID_CORE_RMIDMUX 0 0 1 0
G:JLRCLKOS4_RMID_CORE_RMIDMUX 0 0 1 1
G:JPCLKCIBR0_RMID_CORE_RMIDMUX 0 1 1 0
G:JLRCLKOS2_RMID_CORE_RMIDMUX 0 1 1 1
G:JPCLKT20_RMID_CORE_RMIDMUX 1 0 1 0
G:JPCLKCIBR9_RMID_CORE_RMIDMUX 1 1 0 1
G:JPCLKT12_RMID_CORE_RMIDMUX 1 1 1 0

Mux driving G:JHPFW9_RMID_CORE_RMIDMUX

Source F5B4 F6B4 F7B4 F8B4
G:JPCLKCIBR6_RMID_CORE_RMIDMUX 0 0 1 0
G:JLRCLKOS5_RMID_CORE_RMIDMUX 0 0 1 1
G:JPCLKCIBR1_RMID_CORE_RMIDMUX 0 1 1 0
G:JLRCLKOS2_RMID_CORE_RMIDMUX 0 1 1 1
G:JPCLKT22_RMID_CORE_RMIDMUX 1 0 1 0
G:JPCLKT12_RMID_CORE_RMIDMUX 1 1 1 0

Mux driving W1:JZ_I4_0

Source F15B10
G:JD0_I4_0 -
G:JD1_I4_0 1

Mux driving W1:JZ_I4_1

Source F15B10
G:JD0_I4_1 -
G:JD1_I4_1 1

Mux driving W1:JZ_I4_2

Source F15B10
G:JD0_I4_2 -
G:JD1_I4_2 1

Mux driving W1:JZ_I4_3

Source F15B10
G:JD0_I4_3 -
G:JD1_I4_3 1

Mux driving W1:JZ_I4_4

Source F15B10
G:JD0_I4_4 -
G:JD1_I4_4 1

Mux driving W1:JZ_I4_5

Source F15B10
G:JD0_I4_5 -
G:JD1_I4_5 1

Mux driving W1:JZ_I4_6

Source F15B10
G:JD0_I4_6 -
G:JD1_I4_6 1

Mux driving W1:JZ_I4_7

Source F15B10
G:JD0_I4_7 -
G:JD1_I4_7 1

Mux driving W1:JZ_I4_8

Source F15B10
G:JD0_I4_8 -
G:JD1_I4_8 1

Configuration Words

Configuration word DLLDEL20.ADJUST

DLLDEL20.ADJUST[0]F3B10
DLLDEL20.ADJUST[1]F4B10
DLLDEL20.ADJUST[2]F5B10
DLLDEL20.ADJUST[3]F6B10
DLLDEL20.ADJUST[4]F7B10
DLLDEL20.ADJUST[5]F8B10
DLLDEL20.ADJUST[6]F9B10
DLLDEL20.ADJUST[7]F10B10
DLLDEL20.ADJUST[8]F11B10

Configuration Enums

Configuration enum DCC_R0.DCCEN

DCC bypassed (0) or used as gate (1)

Value F8B1
0 -
1 1

Configuration enum DCC_R1.DCCEN

DCC bypassed (0) or used as gate (1)

Value F7B1
0 -
1 1

Configuration enum DCC_R10.DCCEN

DCC bypassed (0) or used as gate (1)

Value F14B2
0 -
1 1

Configuration enum DCC_R11.DCCEN

DCC bypassed (0) or used as gate (1)

Value F13B2
0 -
1 1

Configuration enum DCC_R2.DCCEN

DCC bypassed (0) or used as gate (1)

Value F6B1
0 -
1 1

Configuration enum DCC_R3.DCCEN

DCC bypassed (0) or used as gate (1)

Value F5B1
0 -
1 1

Configuration enum DCC_R4.DCCEN

DCC bypassed (0) or used as gate (1)

Value F4B1
0 -
1 1

Configuration enum DCC_R5.DCCEN

DCC bypassed (0) or used as gate (1)

Value F3B1
0 -
1 1

Configuration enum DCC_R6.DCCEN

DCC bypassed (0) or used as gate (1)

Value F2B1
0 -
1 1

Configuration enum DCC_R7.DCCEN

DCC bypassed (0) or used as gate (1)

Value F1B1
0 -
1 1

Configuration enum DCC_R8.DCCEN

DCC bypassed (0) or used as gate (1)

Value F0B1
0 -
1 1

Configuration enum DCC_R9.DCCEN

DCC bypassed (0) or used as gate (1)

Value F15B2
0 -
1 1

Configuration enum DLLDEL20.DEL_ADJUST

Value F12B10
MINUS 1
PLUS -

Fixed Connections

SourceSink
W1:JCLKO_DCC_DCC0→ G:JHPFW0_CMUX_CORE_CMUX0
W1:JCLKO_DCC_DCC0→ G:JHPFW0_CMUX_CORE_CMUX1
W1:JCLKO_DCC_DCC0→ G:JHPFW0_DCSMUX_CORE_DCSMUX0
W1:JCLKO_DCC_DCC0→ G:JHPFW0_DCSMUX_CORE_DCSMUX1
W1:JCLKO_DCC_DCC10→ G:JHPFW10_CMUX_CORE_CMUX0
W1:JCLKO_DCC_DCC10→ G:JHPFW10_CMUX_CORE_CMUX1
W1:JCLKO_DCC_DCC10→ G:JHPFW10_DCSMUX_CORE_DCSMUX0
W1:JCLKO_DCC_DCC10→ G:JHPFW10_DCSMUX_CORE_DCSMUX1
W1:JCLKO_DCC_DCC11→ G:JHPFW11_CMUX_CORE_CMUX0
W1:JCLKO_DCC_DCC11→ G:JHPFW11_CMUX_CORE_CMUX1
W1:JCLKO_DCC_DCC11→ G:JHPFW11_DCSMUX_CORE_DCSMUX0
W1:JCLKO_DCC_DCC11→ G:JHPFW11_DCSMUX_CORE_DCSMUX1
W1:JCLKO_DCC_DCC1→ G:JHPFW1_CMUX_CORE_CMUX0
W1:JCLKO_DCC_DCC1→ G:JHPFW1_CMUX_CORE_CMUX1
W1:JCLKO_DCC_DCC1→ G:JHPFW1_DCSMUX_CORE_DCSMUX0
W1:JCLKO_DCC_DCC1→ G:JHPFW1_DCSMUX_CORE_DCSMUX1
W1:JCLKO_DCC_DCC2→ G:JHPFW2_CMUX_CORE_CMUX0
W1:JCLKO_DCC_DCC2→ G:JHPFW2_CMUX_CORE_CMUX1
W1:JCLKO_DCC_DCC2→ G:JHPFW2_DCSMUX_CORE_DCSMUX0
W1:JCLKO_DCC_DCC2→ G:JHPFW2_DCSMUX_CORE_DCSMUX1
W1:JCLKO_DCC_DCC3→ G:JHPFW3_CMUX_CORE_CMUX0
W1:JCLKO_DCC_DCC3→ G:JHPFW3_CMUX_CORE_CMUX1
W1:JCLKO_DCC_DCC3→ G:JHPFW3_DCSMUX_CORE_DCSMUX0
W1:JCLKO_DCC_DCC3→ G:JHPFW3_DCSMUX_CORE_DCSMUX1
W1:JCLKO_DCC_DCC4→ G:JHPFW4_CMUX_CORE_CMUX0
W1:JCLKO_DCC_DCC4→ G:JHPFW4_CMUX_CORE_CMUX1
W1:JCLKO_DCC_DCC4→ G:JHPFW4_DCSMUX_CORE_DCSMUX0
W1:JCLKO_DCC_DCC4→ G:JHPFW4_DCSMUX_CORE_DCSMUX1
W1:JCLKO_DCC_DCC5→ G:JHPFW5_CMUX_CORE_CMUX0
W1:JCLKO_DCC_DCC5→ G:JHPFW5_CMUX_CORE_CMUX1
W1:JCLKO_DCC_DCC5→ G:JHPFW5_DCSMUX_CORE_DCSMUX0
W1:JCLKO_DCC_DCC5→ G:JHPFW5_DCSMUX_CORE_DCSMUX1
W1:JCLKO_DCC_DCC6→ G:JHPFW6_CMUX_CORE_CMUX0
W1:JCLKO_DCC_DCC6→ G:JHPFW6_CMUX_CORE_CMUX1
W1:JCLKO_DCC_DCC6→ G:JHPFW6_DCSMUX_CORE_DCSMUX0
W1:JCLKO_DCC_DCC6→ G:JHPFW6_DCSMUX_CORE_DCSMUX1
W1:JCLKO_DCC_DCC7→ G:JHPFW7_CMUX_CORE_CMUX0
W1:JCLKO_DCC_DCC7→ G:JHPFW7_CMUX_CORE_CMUX1
W1:JCLKO_DCC_DCC7→ G:JHPFW7_DCSMUX_CORE_DCSMUX0
W1:JCLKO_DCC_DCC7→ G:JHPFW7_DCSMUX_CORE_DCSMUX1
W1:JCLKO_DCC_DCC8→ G:JHPFW8_CMUX_CORE_CMUX0
W1:JCLKO_DCC_DCC8→ G:JHPFW8_CMUX_CORE_CMUX1
W1:JCLKO_DCC_DCC8→ G:JHPFW8_DCSMUX_CORE_DCSMUX0
W1:JCLKO_DCC_DCC8→ G:JHPFW8_DCSMUX_CORE_DCSMUX1
W1:JCLKO_DCC_DCC9→ G:JHPFW9_CMUX_CORE_CMUX0
W1:JCLKO_DCC_DCC9→ G:JHPFW9_CMUX_CORE_CMUX1
W1:JCLKO_DCC_DCC9→ G:JHPFW9_DCSMUX_CORE_DCSMUX0
W1:JCLKO_DCC_DCC9→ G:JHPFW9_DCSMUX_CORE_DCSMUX1
N2W1:JCIBMUXOUTD7→ G:JPCLKCIBR0_RMID_CORE_RMIDMUX
N1W1:JCIBMUXOUTC7→ G:JPCLKCIBR1_RMID_CORE_RMIDMUX
S1W1:JCIBMUXOUTC7→ G:JPCLKCIBR2_RMID_CORE_RMIDMUX
S2W1:JCIBMUXOUTC7→ G:JPCLKCIBR3_RMID_CORE_RMIDMUX
N18W13:JCIBMUXOUTD7→ G:JPCLKCIBR4_RMID_CORE_RMIDMUX
N9W13:JCIBMUXOUTD7→ G:JPCLKCIBR5_RMID_CORE_RMIDMUX
S9W13:JCIBMUXOUTD7→ G:JPCLKCIBR6_RMID_CORE_RMIDMUX
S18W13:JCIBMUXOUTD7→ G:JPCLKCIBR7_RMID_CORE_RMIDMUX
N9W13:JCIBMUXOUTD6→ G:JPCLKCIBR8_RMID_CORE_RMIDMUX
S9W13:JCIBMUXOUTD6→ G:JPCLKCIBR9_RMID_CORE_RMIDMUX
N7W1:JCLKOUT_DLLDEL_CORE_I0→ G:JPCLKT10_RMID_CORE_RMIDMUX
N9:JINCK_SIOLOGIC_CORE_IBASE_PIC_A→ G:JPCLKT11_RMID_CORE_RMIDMUX
N9:JPADDI_SEIO33_CORE_IOA→ G:JPCLKT11_RMID_CORE_RMIDMUX
N11:JINCK_SIOLOGIC_CORE_IBASE_PIC_A→ G:JPCLKT12_RMID_CORE_RMIDMUX
N11:JPADDI_SEIO33_CORE_IOA→ G:JPCLKT12_RMID_CORE_RMIDMUX
W1:JCLKOUT_DLLDEL_CORE_I0→ G:JPCLKT20_RMID_CORE_RMIDMUX
S4:JINCK_SIOLOGIC_CORE_IBASE_PIC_A→ G:JPCLKT21_RMID_CORE_RMIDMUX
S4:JPADDI_SEIO33_CORE_IOA→ G:JPCLKT21_RMID_CORE_RMIDMUX
S6:JINCK_SIOLOGIC_CORE_IBASE_PIC_A→ G:JPCLKT22_RMID_CORE_RMIDMUX
S6:JPADDI_SEIO33_CORE_IOA→ G:JPCLKT22_RMID_CORE_RMIDMUX
W1:JCIBMUXOUTA0→ G:JTESTINP0_RMID_CORE_RMIDMUX
W1:JCIBMUXOUTA1→ G:JTESTINP1_RMID_CORE_RMIDMUX
W1:JCIBMUXOUTA2→ G:JTESTINP2_RMID_CORE_RMIDMUX
W1:JCIBMUXOUTA3→ G:JTESTINP3_RMID_CORE_RMIDMUX
W1:JCIBMUXOUTC5→ W1:JBYPASS_DLLDEL_CORE_I0
W1:JCIBMUXOUTB0→ W1:JCE_DCC_DCC0
W1:JCIBMUXOUTB1→ W1:JCE_DCC_DCC1
W1:JCIBMUXOUTD5→ W1:JCE_DCC_DCC10
W1:JCIBMUXOUTD6→ W1:JCE_DCC_DCC11
W1:JCIBMUXOUTB2→ W1:JCE_DCC_DCC2
W1:JCIBMUXOUTB3→ W1:JCE_DCC_DCC3
W1:JCIBMUXOUTB4→ W1:JCE_DCC_DCC4
W1:JCIBMUXOUTB5→ W1:JCE_DCC_DCC5
W1:JCIBMUXOUTB6→ W1:JCE_DCC_DCC6
W1:JCIBMUXOUTB7→ W1:JCE_DCC_DCC7
W1:JCIBMUXOUTD3→ W1:JCE_DCC_DCC8
W1:JCIBMUXOUTD4→ W1:JCE_DCC_DCC9
S2:JINCK_SIOLOGIC_CORE_IBASE_PIC_A→ W1:JCLKIN_DLLDEL_CORE_I0
S2:JPADDI_SEIO33_CORE_IOA→ W1:JCLKIN_DLLDEL_CORE_I0
G:JHPFW0_RMID_CORE_RMIDMUX→ W1:JCLKI_DCC_DCC0
G:JHPFW1_RMID_CORE_RMIDMUX→ W1:JCLKI_DCC_DCC1
G:JHPFW10_RMID_CORE_RMIDMUX→ W1:JCLKI_DCC_DCC10
G:JHPFW11_RMID_CORE_RMIDMUX→ W1:JCLKI_DCC_DCC11
G:JHPFW2_RMID_CORE_RMIDMUX→ W1:JCLKI_DCC_DCC2
G:JHPFW3_RMID_CORE_RMIDMUX→ W1:JCLKI_DCC_DCC3
G:JHPFW4_RMID_CORE_RMIDMUX→ W1:JCLKI_DCC_DCC4
G:JHPFW5_RMID_CORE_RMIDMUX→ W1:JCLKI_DCC_DCC5
G:JHPFW6_RMID_CORE_RMIDMUX→ W1:JCLKI_DCC_DCC6
G:JHPFW7_RMID_CORE_RMIDMUX→ W1:JCLKI_DCC_DCC7
G:JHPFW8_RMID_CORE_RMIDMUX→ W1:JCLKI_DCC_DCC8
G:JHPFW9_RMID_CORE_RMIDMUX→ W1:JCLKI_DCC_DCC9
W1:JCLKI_DCC_DCC0→ W1:JCLKO_DCC_DCC0
W1:JCLKI_DCC_DCC1→ W1:JCLKO_DCC_DCC1
W1:JCLKI_DCC_DCC10→ W1:JCLKO_DCC_DCC10
W1:JCLKI_DCC_DCC11→ W1:JCLKO_DCC_DCC11
W1:JCLKI_DCC_DCC2→ W1:JCLKO_DCC_DCC2
W1:JCLKI_DCC_DCC3→ W1:JCLKO_DCC_DCC3
W1:JCLKI_DCC_DCC4→ W1:JCLKO_DCC_DCC4
W1:JCLKI_DCC_DCC5→ W1:JCLKO_DCC_DCC5
W1:JCLKI_DCC_DCC6→ W1:JCLKO_DCC_DCC6
W1:JCLKI_DCC_DCC7→ W1:JCLKO_DCC_DCC7
W1:JCLKI_DCC_DCC8→ W1:JCLKO_DCC_DCC8
W1:JCLKI_DCC_DCC9→ W1:JCLKO_DCC_DCC9
W1:JZ_I4_0→ W1:JCODE0_DLLDEL_CORE_I0
W1:JZ_I4_1→ W1:JCODE1_DLLDEL_CORE_I0
W1:JZ_I4_2→ W1:JCODE2_DLLDEL_CORE_I0
W1:JZ_I4_3→ W1:JCODE3_DLLDEL_CORE_I0
W1:JZ_I4_4→ W1:JCODE4_DLLDEL_CORE_I0
W1:JZ_I4_5→ W1:JCODE5_DLLDEL_CORE_I0
W1:JZ_I4_6→ W1:JCODE6_DLLDEL_CORE_I0
W1:JZ_I4_7→ W1:JCODE7_DLLDEL_CORE_I0
W1:JZ_I4_8→ W1:JCODE8_DLLDEL_CORE_I0
W1:JCIBMUXOUTD7→ W1:JDIR_DLLDEL_CORE_I0
W1:JCIBMUXOUTD1→ W1:JLOAD_N_DLLDEL_CORE_I0
W1:JCIBMUXOUTC6→ W1:JMOVE_DLLDEL_CORE_I0
W1:JCOUT_DLLDEL_CORE_I0→ W1:JQ6