| Name | Type |
|---|---|
| LRAM1 | LRAM_CORE |
|
C |
C |
C |
S |
G |
A |
B |
P |
R |
R |
R |
R |
1 |
W |
W |
E |
|
|
|
|
|
|
|
|
|
|
|
E |
|
E |
R |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
LRAM reset release configuration
| Value | F10B0 |
|---|---|
| ASYNC | 1 |
| SYNC | - |
LRAM CLK inversion control
| Value | F0B0 |
|---|---|
| CLK | - |
| INV | 1 |
LRAM CSA inversion control
| Value | F1B0 |
|---|---|
| CSA | - |
| INV | 1 |
LRAM CSB inversion control
| Value | F2B0 |
|---|---|
| CSB | - |
| INV | 1 |
LRAM data preservation across resets
| Value | F7B0 |
|---|---|
| DISABLE | - |
| ENABLE | 1 |
EBR single port mode
| Value | F10B1 |
|---|---|
| DISABLE | - |
| ENABLE | 1 |
| Value | F3B0 |
|---|---|
| BYTE_EN | 1 |
| ECC_EN | - |
LRAM global set/reset mask
| Value | F4B0 |
|---|---|
| DISABLED | 1 |
| ENABLED | - |
LRAM output pipeline register A enable
| Value | F5B0 |
|---|---|
| NO_REG | - |
| OUT_REG | 1 |
LRAM output pipeline register B enable
| Value | F6B0 |
|---|---|
| NO_REG | - |
| OUT_REG | 1 |
LRAM sync/async reset select
| Value | F13B1 |
|---|---|
| ASYNC | 1 |
| SYNC | - |
LRAM RSTA inversion control
| Value | F8B0 |
|---|---|
| INV | 1 |
| RSTA | - |
LRAM RSTB inversion control
| Value | F9B0 |
|---|---|
| INV | 1 |
| RSTB | - |
LRAM reset A/B enable
| Value | F15B0 |
|---|---|
| RESET_AB_DISABLE | - |
| RESET_AB_ENABLE | 1 |
LRAM single port mode
| Value | F12B1 |
|---|---|
| DISABLE | - |
| ENABLE | 1 |
LRAM unaligned read support
| Value | F11B0 |
|---|---|
| DISABLE | - |
| ENABLE | 1 |
LRAM WEA inversion control
| Value | F13B0 |
|---|---|
| INV | 1 |
| WEA | - |
LRAM WEB inversion control
| Value | F14B0 |
|---|---|
| INV | 1 |
| WEB | - |
| Source | Sink | |
|---|---|---|
| S7W1:JCIBMUXOUTD0 | → | N1W1:JADA0_LRAM_CORE |
| S7W1:JCIBMUXOUTB3 | → | N1W1:JADA10_LRAM_CORE |
| S7W1:JCIBMUXOUTA1 | → | N1W1:JADA11_LRAM_CORE |
| S7W1:JCIBMUXOUTB5 | → | N1W1:JADA12_LRAM_CORE |
| S7W1:JCIBMUXOUTB7 | → | N1W1:JADA13_LRAM_CORE |
| S7W1:JCIBMUXOUTC7 | → | N1W1:JADA1_LRAM_CORE |
| S7W1:JCIBMUXOUTC6 | → | N1W1:JADA2_LRAM_CORE |
| S7W1:JCIBMUXOUTC5 | → | N1W1:JADA3_LRAM_CORE |
| S7W1:JCIBMUXOUTA6 | → | N1W1:JADA4_LRAM_CORE |
| S7W1:JCIBMUXOUTA2 | → | N1W1:JADA5_LRAM_CORE |
| S7W1:JCIBMUXOUTA0 | → | N1W1:JADA6_LRAM_CORE |
| S7W1:JCIBMUXOUTB2 | → | N1W1:JADA7_LRAM_CORE |
| S7W1:JCIBMUXOUTA4 | → | N1W1:JADA8_LRAM_CORE |
| S7W1:JCIBMUXOUTB0 | → | N1W1:JADA9_LRAM_CORE |
| S2W1:JCIBMUXOUTC0 | → | N1W1:JADB0_LRAM_CORE |
| W1:JCIBMUXOUTA5 | → | N1W1:JADB10_LRAM_CORE |
| W1:JCIBMUXOUTD2 | → | N1W1:JADB11_LRAM_CORE |
| W1:JCIBMUXOUTD1 | → | N1W1:JADB12_LRAM_CORE |
| W1:JCIBMUXOUTD0 | → | N1W1:JADB13_LRAM_CORE |
| S2W1:JCIBMUXOUTC1 | → | N1W1:JADB1_LRAM_CORE |
| S2W1:JCIBMUXOUTC2 | → | N1W1:JADB2_LRAM_CORE |
| S2W1:JCIBMUXOUTC3 | → | N1W1:JADB3_LRAM_CORE |
| S2W1:JCIBMUXOUTC4 | → | N1W1:JADB4_LRAM_CORE |
| W1:JCIBMUXOUTB6 | → | N1W1:JADB5_LRAM_CORE |
| W1:JCIBMUXOUTD7 | → | N1W1:JADB6_LRAM_CORE |
| W1:JCIBMUXOUTD6 | → | N1W1:JADB7_LRAM_CORE |
| W1:JCIBMUXOUTD5 | → | N1W1:JADB8_LRAM_CORE |
| W1:JCIBMUXOUTD4 | → | N1W1:JADB9_LRAM_CORE |
| S7W1:JCIBMUXOUTB6 | → | N1W1:JBENA_N0_LRAM_CORE |
| S7W1:JCIBMUXOUTD7 | → | N1W1:JBENA_N1_LRAM_CORE |
| S7W1:JCIBMUXOUTD6 | → | N1W1:JBENA_N2_LRAM_CORE |
| S7W1:JCIBMUXOUTD5 | → | N1W1:JBENA_N3_LRAM_CORE |
| S7W1:JCIBMUXOUTD4 | → | N1W1:JBENB_N0_LRAM_CORE |
| S7W1:JCIBMUXOUTA5 | → | N1W1:JBENB_N1_LRAM_CORE |
| S7W1:JCIBMUXOUTD2 | → | N1W1:JBENB_N2_LRAM_CORE |
| S7W1:JCIBMUXOUTD1 | → | N1W1:JBENB_N3_LRAM_CORE |
| S4W1:JCE0 | → | N1W1:JCEA_LRAM_CORE |
| S2W1:JCE0 | → | N1W1:JCEB_LRAM_CORE |
| S4W1:JCLK0 | → | N1W1:JCLK_LRAM_CORE |
| S2W1:JCIBMUXOUTD3 | → | N1W1:JCSA_LRAM_CORE |
| S2W1:JCIBMUXOUTB1 | → | N1W1:JCSB_LRAM_CORE |
| S7W1:JCIBMUXOUTD3 | → | N1W1:JDIA0_LRAM_CORE |
| S4W1:JCIBMUXOUTB6 | → | N1W1:JDIA10_LRAM_CORE |
| S4W1:JCIBMUXOUTD7 | → | N1W1:JDIA11_LRAM_CORE |
| S4W1:JCIBMUXOUTD6 | → | N1W1:JDIA12_LRAM_CORE |
| S4W1:JCIBMUXOUTD5 | → | N1W1:JDIA13_LRAM_CORE |
| S4W1:JCIBMUXOUTD4 | → | N1W1:JDIA14_LRAM_CORE |
| S4W1:JCIBMUXOUTA5 | → | N1W1:JDIA15_LRAM_CORE |
| S4W1:JCIBMUXOUTD2 | → | N1W1:JDIA16_LRAM_CORE |
| S4W1:JCIBMUXOUTD1 | → | N1W1:JDIA17_LRAM_CORE |
| S4W1:JCIBMUXOUTD0 | → | N1W1:JDIA18_LRAM_CORE |
| S4W1:JCIBMUXOUTC7 | → | N1W1:JDIA19_LRAM_CORE |
| S7W1:JCIBMUXOUTB1 | → | N1W1:JDIA1_LRAM_CORE |
| S4W1:JCIBMUXOUTC6 | → | N1W1:JDIA20_LRAM_CORE |
| S4W1:JCIBMUXOUTC5 | → | N1W1:JDIA21_LRAM_CORE |
| S4W1:JCIBMUXOUTA6 | → | N1W1:JDIA22_LRAM_CORE |
| S4W1:JCIBMUXOUTA2 | → | N1W1:JDIA23_LRAM_CORE |
| S4W1:JCIBMUXOUTA0 | → | N1W1:JDIA24_LRAM_CORE |
| S4W1:JCIBMUXOUTB2 | → | N1W1:JDIA25_LRAM_CORE |
| S4W1:JCIBMUXOUTA4 | → | N1W1:JDIA26_LRAM_CORE |
| S4W1:JCIBMUXOUTB0 | → | N1W1:JDIA27_LRAM_CORE |
| S4W1:JCIBMUXOUTB3 | → | N1W1:JDIA28_LRAM_CORE |
| S4W1:JCIBMUXOUTA1 | → | N1W1:JDIA29_LRAM_CORE |
| S7W1:JCIBMUXOUTA3 | → | N1W1:JDIA2_LRAM_CORE |
| S4W1:JCIBMUXOUTB5 | → | N1W1:JDIA30_LRAM_CORE |
| S4W1:JCIBMUXOUTB7 | → | N1W1:JDIA31_LRAM_CORE |
| S7W1:JCIBMUXOUTA7 | → | N1W1:JDIA3_LRAM_CORE |
| S7W1:JCIBMUXOUTB4 | → | N1W1:JDIA4_LRAM_CORE |
| S7W1:JCIBMUXOUTC0 | → | N1W1:JDIA5_LRAM_CORE |
| S7W1:JCIBMUXOUTC1 | → | N1W1:JDIA6_LRAM_CORE |
| S7W1:JCIBMUXOUTC2 | → | N1W1:JDIA7_LRAM_CORE |
| S7W1:JCIBMUXOUTC3 | → | N1W1:JDIA8_LRAM_CORE |
| S7W1:JCIBMUXOUTC4 | → | N1W1:JDIA9_LRAM_CORE |
| S4W1:JCIBMUXOUTD3 | → | N1W1:JDIB0_LRAM_CORE |
| S2W1:JCIBMUXOUTB6 | → | N1W1:JDIB10_LRAM_CORE |
| S2W1:JCIBMUXOUTD7 | → | N1W1:JDIB11_LRAM_CORE |
| S2W1:JCIBMUXOUTD6 | → | N1W1:JDIB12_LRAM_CORE |
| S2W1:JCIBMUXOUTD5 | → | N1W1:JDIB13_LRAM_CORE |
| S2W1:JCIBMUXOUTD4 | → | N1W1:JDIB14_LRAM_CORE |
| S2W1:JCIBMUXOUTA5 | → | N1W1:JDIB15_LRAM_CORE |
| S2W1:JCIBMUXOUTD2 | → | N1W1:JDIB16_LRAM_CORE |
| S2W1:JCIBMUXOUTD1 | → | N1W1:JDIB17_LRAM_CORE |
| S2W1:JCIBMUXOUTD0 | → | N1W1:JDIB18_LRAM_CORE |
| S2W1:JCIBMUXOUTC7 | → | N1W1:JDIB19_LRAM_CORE |
| S4W1:JCIBMUXOUTB1 | → | N1W1:JDIB1_LRAM_CORE |
| S2W1:JCIBMUXOUTC6 | → | N1W1:JDIB20_LRAM_CORE |
| S2W1:JCIBMUXOUTC5 | → | N1W1:JDIB21_LRAM_CORE |
| S2W1:JCIBMUXOUTA6 | → | N1W1:JDIB22_LRAM_CORE |
| S2W1:JCIBMUXOUTA2 | → | N1W1:JDIB23_LRAM_CORE |
| S2W1:JCIBMUXOUTA0 | → | N1W1:JDIB24_LRAM_CORE |
| S2W1:JCIBMUXOUTB2 | → | N1W1:JDIB25_LRAM_CORE |
| S2W1:JCIBMUXOUTA4 | → | N1W1:JDIB26_LRAM_CORE |
| S2W1:JCIBMUXOUTB0 | → | N1W1:JDIB27_LRAM_CORE |
| S2W1:JCIBMUXOUTB3 | → | N1W1:JDIB28_LRAM_CORE |
| S2W1:JCIBMUXOUTA1 | → | N1W1:JDIB29_LRAM_CORE |
| S4W1:JCIBMUXOUTA3 | → | N1W1:JDIB2_LRAM_CORE |
| S2W1:JCIBMUXOUTB5 | → | N1W1:JDIB30_LRAM_CORE |
| S2W1:JCIBMUXOUTB7 | → | N1W1:JDIB31_LRAM_CORE |
| S4W1:JCIBMUXOUTA7 | → | N1W1:JDIB3_LRAM_CORE |
| S4W1:JCIBMUXOUTB4 | → | N1W1:JDIB4_LRAM_CORE |
| S4W1:JCIBMUXOUTC0 | → | N1W1:JDIB5_LRAM_CORE |
| S4W1:JCIBMUXOUTC1 | → | N1W1:JDIB6_LRAM_CORE |
| S4W1:JCIBMUXOUTC2 | → | N1W1:JDIB7_LRAM_CORE |
| S4W1:JCIBMUXOUTC3 | → | N1W1:JDIB8_LRAM_CORE |
| S4W1:JCIBMUXOUTC4 | → | N1W1:JDIB9_LRAM_CORE |
| S2W1:JCIBMUXOUTB4 | → | N1W1:JDPS_LRAM_CORE |
| N1W1:JOEB_LRAM_CORE | → | N1W1:JF2 |
| W1:JCIBMUXOUTC7 | → | N1W1:JIGN_LRAM_CORE |
| W1:JCIBMUXOUTC6 | → | N1W1:JINITN_LRAM_CORE |
| S2W1:JCE1 | → | N1W1:JOCEA_LRAM_CORE |
| W1:JCE1 | → | N1W1:JOCEB_LRAM_CORE |
| W1:JCLK1 | → | N1W1:JOPCGLOADCLK_LRAM_CORE |
| N1W1:JOEA_LRAM_CORE | → | N1W1:JQ2 |
| N1W1:JLRAMREADY_LRAM_CORE | → | N1W1:JQ3 |
| N1W1:JDOB31_LRAM_CORE | → | N1W1:JQ6 |
| N1W1:JDOB30_LRAM_CORE | → | N1W1:JQ7 |
| S4W1:JLSR0 | → | N1W1:JRSTA_LRAM_CORE |
| S2W1:JLSR0 | → | N1W1:JRSTB_LRAM_CORE |
| W1:JCLK0 | → | N1W1:JSCANCLK_LRAM_CORE |
| W1:JLSR0 | → | N1W1:JSCANRST_LRAM_CORE |
| W1:JCIBMUXOUTC5 | → | N1W1:JSTDBYN_LRAM_CORE |
| W1:JCIBMUXOUTA6 | → | N1W1:JTBISTN_LRAM_CORE |
| S2W1:JCIBMUXOUTA3 | → | N1W1:JWEA_LRAM_CORE |
| S2W1:JCIBMUXOUTA7 | → | N1W1:JWEB_LRAM_CORE |
| N1W1:JDOB13_LRAM_CORE | → | S1W1:JQ2 |
| N1W1:JDOB12_LRAM_CORE | → | S1W1:JQ6 |
| N1W1:JDOB6_LRAM_CORE | → | S2W1:JF0 |
| N1W1:JDOB7_LRAM_CORE | → | S2W1:JF1 |
| N1W1:JDOB8_LRAM_CORE | → | S2W1:JF2 |
| N1W1:JDOB9_LRAM_CORE | → | S2W1:JF3 |
| N1W1:JDOB10_LRAM_CORE | → | S2W1:JF4 |
| N1W1:JDOB11_LRAM_CORE | → | S2W1:JF5 |
| N1W1:JDOA30_LRAM_CORE | → | S2W1:JF6 |
| N1W1:JDOA29_LRAM_CORE | → | S2W1:JF7 |
| N1W1:JDOB5_LRAM_CORE | → | S2W1:JQ0 |
| N1W1:JDOB4_LRAM_CORE | → | S2W1:JQ1 |
| N1W1:JDOB3_LRAM_CORE | → | S2W1:JQ2 |
| N1W1:JDOB2_LRAM_CORE | → | S2W1:JQ3 |
| N1W1:JDOB1_LRAM_CORE | → | S2W1:JQ4 |
| N1W1:JDOB0_LRAM_CORE | → | S2W1:JQ5 |
| N1W1:JDOA31_LRAM_CORE | → | S2W1:JQ6 |
| N1W1:JDOA28_LRAM_CORE | → | S2W1:JQ7 |
| N1W1:JDOA27_LRAM_CORE | → | S3W1:JF2 |
| N1W1:JDOA21_LRAM_CORE | → | S4W1:JF0 |
| N1W1:JDOA22_LRAM_CORE | → | S4W1:JF1 |
| N1W1:JDOA23_LRAM_CORE | → | S4W1:JF2 |
| N1W1:JDOA24_LRAM_CORE | → | S4W1:JF3 |
| N1W1:JDOA25_LRAM_CORE | → | S4W1:JF4 |
| N1W1:JDOA26_LRAM_CORE | → | S4W1:JF5 |
| N1W1:JDOA13_LRAM_CORE | → | S4W1:JF6 |
| N1W1:JDOA12_LRAM_CORE | → | S4W1:JF7 |
| N1W1:JDOA20_LRAM_CORE | → | S4W1:JQ0 |
| N1W1:JDOA19_LRAM_CORE | → | S4W1:JQ1 |
| N1W1:JDOA18_LRAM_CORE | → | S4W1:JQ2 |
| N1W1:JDOA17_LRAM_CORE | → | S4W1:JQ3 |
| N1W1:JDOA16_LRAM_CORE | → | S4W1:JQ4 |
| N1W1:JDOA15_LRAM_CORE | → | S4W1:JQ5 |
| N1W1:JDOA14_LRAM_CORE | → | S4W1:JQ6 |
| N1W1:JDOA11_LRAM_CORE | → | S4W1:JQ7 |
| N1W1:JDOA10_LRAM_CORE | → | S6W1:JQ2 |
| N1W1:JDOA9_LRAM_CORE | → | S6W1:JQ3 |
| N1W1:JDOA8_LRAM_CORE | → | S6W1:JQ6 |
| N1W1:JDOA2_LRAM_CORE | → | S7W1:JF0 |
| N1W1:JDOA3_LRAM_CORE | → | S7W1:JF1 |
| N1W1:JDOA4_LRAM_CORE | → | S7W1:JF2 |
| N1W1:JDOA5_LRAM_CORE | → | S7W1:JF3 |
| N1W1:JDOA6_LRAM_CORE | → | S7W1:JF4 |
| N1W1:JDOA7_LRAM_CORE | → | S7W1:JF5 |
| N1W1:JERRDECA1_LRAM_CORE | → | S7W1:JF6 |
| N1W1:JERRDECA0_LRAM_CORE | → | S7W1:JF7 |
| N1W1:JDOA1_LRAM_CORE | → | S7W1:JQ3 |
| N1W1:JDOA0_LRAM_CORE | → | S7W1:JQ4 |
| N1W1:JERRDECB1_LRAM_CORE | → | S7W1:JQ5 |
| N1W1:JERRDECB0_LRAM_CORE | → | S7W1:JQ6 |
| N1W1:JERRDET_LRAM_CORE | → | S7W1:JQ7 |
| N1W1:JDOB24_LRAM_CORE | → | W1:JF0 |
| N1W1:JDOB25_LRAM_CORE | → | W1:JF1 |
| N1W1:JDOB26_LRAM_CORE | → | W1:JF2 |
| N1W1:JDOB27_LRAM_CORE | → | W1:JF3 |
| N1W1:JDOB28_LRAM_CORE | → | W1:JF4 |
| N1W1:JDOB29_LRAM_CORE | → | W1:JF5 |
| N1W1:JDOB16_LRAM_CORE | → | W1:JF6 |
| N1W1:JDOB15_LRAM_CORE | → | W1:JF7 |
| N1W1:JDOB23_LRAM_CORE | → | W1:JQ0 |
| N1W1:JDOB22_LRAM_CORE | → | W1:JQ1 |
| N1W1:JDOB21_LRAM_CORE | → | W1:JQ2 |
| N1W1:JDOB20_LRAM_CORE | → | W1:JQ3 |
| N1W1:JDOB19_LRAM_CORE | → | W1:JQ4 |
| N1W1:JDOB18_LRAM_CORE | → | W1:JQ5 |
| N1W1:JDOB17_LRAM_CORE | → | W1:JQ6 |
| N1W1:JDOB14_LRAM_CORE | → | W1:JQ7 |