LMID_RBB_5_15K Tile Documentation

Tile Bels

NameType
DCC_L0 DCC
DCC_L1 DCC
DCC_L2 DCC
DCC_L3 DCC
DCC_L4 DCC
DCC_L5 DCC
DCC_L6 DCC
DCC_L7 DCC
DCC_L8 DCC
DCC_L9 DCC
DCC_L10 DCC
DCC_L11 DCC

Config Bitmap

1
 
1
 
1
 
 
1
 
1
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
1
 
 
 
1
1
 
 
 
1
1
1
 
 
1
1
 
 
1
1
 
 
 
 
 
 
 
 
 
 
 
1
 
1
 
1
 
 
1
 
1
 
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
D
D
D
D
D
D
D
D
D
D
D
D
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
 
 
 

Routing Muxes

Mux driving G:JHPFE0_LMID_CORE_LMIDMUX

Source F0B8 F13B7 F14B7 F15B7
G:JPCLKCIBL4_LMID_CORE_LMIDMUX 0 0 1 0
G:JPCLKCIBL0_LMID_CORE_LMIDMUX 0 0 1 1
G:JLLCLKOS3_LMID_CORE_LMIDMUX 0 1 1 0
G:JLLCLKOS_LMID_CORE_LMIDMUX 0 1 1 1
G:JSGMIICLK0_LMID_CORE_LMIDMUX 1 1 0 1

Mux driving G:JHPFE10_LMID_CORE_LMIDMUX

Source F5B10 F6B10 F7B10 F8B10
G:JPCLKCIBL8_LMID_CORE_LMIDMUX 0 1 0 0
G:JPCLKCIBL1_LMID_CORE_LMIDMUX 0 1 1 0
G:JSGMIICLK0_LMID_CORE_LMIDMUX 1 0 1 1
G:JLLCLKOS_LMID_CORE_LMIDMUX 1 1 0 0
G:JLLCLKOP_LMID_CORE_LMIDMUX 1 1 1 0

Mux driving G:JHPFE11_LMID_CORE_LMIDMUX

Source F9B10 F10B10 F11B10 F12B10
G:JPCLKCIBL7_LMID_CORE_LMIDMUX 0 1 0 0
G:JPCLKCIBL3_LMID_CORE_LMIDMUX 0 1 1 0
G:JPCLKCIBL9_LMID_CORE_LMIDMUX 1 0 1 1
G:JLLCLKOS3_LMID_CORE_LMIDMUX 1 1 0 0
G:JLLCLKOS_LMID_CORE_LMIDMUX 1 1 1 0

Mux driving G:JHPFE1_LMID_CORE_LMIDMUX

Source F1B8 F2B8 F3B8 F4B8
G:JPCLKCIBL5_LMID_CORE_LMIDMUX 0 1 0 0
G:JPCLKCIBL1_LMID_CORE_LMIDMUX 0 1 1 0
G:JSGMIICLK1_LMID_CORE_LMIDMUX 1 0 0 1
G:JPCLKCIBL9_LMID_CORE_LMIDMUX 1 0 1 1
G:JLLCLKOS4_LMID_CORE_LMIDMUX 1 1 0 0
G:JLLCLKOP_LMID_CORE_LMIDMUX 1 1 1 0

Mux driving G:JHPFE2_LMID_CORE_LMIDMUX

Source F5B8 F6B8 F7B8 F8B8
G:JPCLKCIBL6_LMID_CORE_LMIDMUX 0 1 0 0
G:JPCLKCIBL2_LMID_CORE_LMIDMUX 0 1 1 0
G:JPCLKCIBL8_LMID_CORE_LMIDMUX 1 0 1 1
G:JLLCLKOS4_LMID_CORE_LMIDMUX 1 1 0 0
G:JLLCLKOS_LMID_CORE_LMIDMUX 1 1 1 0

Mux driving G:JHPFE3_LMID_CORE_LMIDMUX

Source F9B8 F10B8 F11B8 F12B8
G:JPCLKCIBL7_LMID_CORE_LMIDMUX 0 1 0 0
G:JPCLKCIBL3_LMID_CORE_LMIDMUX 0 1 1 0
G:JSGMIICLK1_LMID_CORE_LMIDMUX 1 0 0 1
G:JPCLKCIBL9_LMID_CORE_LMIDMUX 1 0 1 1
G:JLLCLKOS5_LMID_CORE_LMIDMUX 1 1 0 0
G:JLLCLKOS3_LMID_CORE_LMIDMUX 1 1 1 0

Mux driving G:JHPFE4_LMID_CORE_LMIDMUX

Source F0B9 F13B8 F14B8 F15B8
G:JPCLKCIBL6_LMID_CORE_LMIDMUX 0 0 1 0
G:JPCLKCIBL4_LMID_CORE_LMIDMUX 0 0 1 1
G:JLLCLKOS4_LMID_CORE_LMIDMUX 0 1 1 0
G:JLLCLKOS2_LMID_CORE_LMIDMUX 0 1 1 1
G:JPCLKCIBL8_LMID_CORE_LMIDMUX 1 1 0 1

Mux driving G:JHPFE5_LMID_CORE_LMIDMUX

Source F1B9 F2B9 F3B9 F4B9
G:JPCLKCIBL7_LMID_CORE_LMIDMUX 0 1 0 0
G:JPCLKCIBL2_LMID_CORE_LMIDMUX 0 1 1 0
G:JSGMIICLK0_LMID_CORE_LMIDMUX 1 0 1 1
G:JLLCLKOS3_LMID_CORE_LMIDMUX 1 1 0 0
G:JLLCLKOP_LMID_CORE_LMIDMUX 1 1 1 0

Mux driving G:JHPFE6_LMID_CORE_LMIDMUX

Source F5B9 F6B9 F7B9 F8B9
G:JPCLKCIBL5_LMID_CORE_LMIDMUX 0 1 0 0
G:JPCLKCIBL3_LMID_CORE_LMIDMUX 0 1 1 0
G:JSGMIICLK1_LMID_CORE_LMIDMUX 1 0 0 1
G:JPCLKCIBL8_LMID_CORE_LMIDMUX 1 0 1 1
G:JLLCLKOS5_LMID_CORE_LMIDMUX 1 1 0 0
G:JLLCLKOS2_LMID_CORE_LMIDMUX 1 1 1 0

Mux driving G:JHPFE7_LMID_CORE_LMIDMUX

Source F9B9 F10B9 F11B9 F12B9
G:JPCLKCIBL2_LMID_CORE_LMIDMUX 0 1 0 0
G:JPCLKCIBL0_LMID_CORE_LMIDMUX 0 1 1 0
G:JPCLKCIBL5_LMID_CORE_LMIDMUX 1 0 1 1
G:JLLCLKOS5_LMID_CORE_LMIDMUX 1 1 0 0
G:JLLCLKOP_LMID_CORE_LMIDMUX 1 1 1 0

Mux driving G:JHPFE8_LMID_CORE_LMIDMUX

Source F0B10 F13B9 F14B9 F15B9
G:JPCLKCIBL4_LMID_CORE_LMIDMUX 0 0 1 0
G:JPCLKCIBL0_LMID_CORE_LMIDMUX 0 0 1 1
G:JLLCLKOS4_LMID_CORE_LMIDMUX 0 1 1 0
G:JLLCLKOS2_LMID_CORE_LMIDMUX 0 1 1 1
G:JSGMIICLK1_LMID_CORE_LMIDMUX 1 1 0 0
G:JPCLKCIBL9_LMID_CORE_LMIDMUX 1 1 0 1

Mux driving G:JHPFE9_LMID_CORE_LMIDMUX

Source F1B10 F2B10 F3B10 F4B10
G:JPCLKCIBL6_LMID_CORE_LMIDMUX 0 1 0 0
G:JPCLKCIBL1_LMID_CORE_LMIDMUX 0 1 1 0
G:JSGMIICLK0_LMID_CORE_LMIDMUX 1 0 1 1
G:JLLCLKOS5_LMID_CORE_LMIDMUX 1 1 0 0
G:JLLCLKOS2_LMID_CORE_LMIDMUX 1 1 1 0

Configuration Enums

Configuration enum DCC_L0.DCCEN

DCC bypassed (0) or used as gate (1)

Value F1B7
0 -
1 1

Configuration enum DCC_L1.DCCEN

DCC bypassed (0) or used as gate (1)

Value F2B7
0 -
1 1

Configuration enum DCC_L10.DCCEN

DCC bypassed (0) or used as gate (1)

Value F11B7
0 -
1 1

Configuration enum DCC_L11.DCCEN

DCC bypassed (0) or used as gate (1)

Value F12B7
0 -
1 1

Configuration enum DCC_L2.DCCEN

DCC bypassed (0) or used as gate (1)

Value F3B7
0 -
1 1

Configuration enum DCC_L3.DCCEN

DCC bypassed (0) or used as gate (1)

Value F4B7
0 -
1 1

Configuration enum DCC_L4.DCCEN

DCC bypassed (0) or used as gate (1)

Value F5B7
0 -
1 1

Configuration enum DCC_L5.DCCEN

DCC bypassed (0) or used as gate (1)

Value F6B7
0 -
1 1

Configuration enum DCC_L6.DCCEN

DCC bypassed (0) or used as gate (1)

Value F7B7
0 -
1 1

Configuration enum DCC_L7.DCCEN

DCC bypassed (0) or used as gate (1)

Value F8B7
0 -
1 1

Configuration enum DCC_L8.DCCEN

DCC bypassed (0) or used as gate (1)

Value F9B7
0 -
1 1

Configuration enum DCC_L9.DCCEN

DCC bypassed (0) or used as gate (1)

Value F10B7
0 -
1 1

Fixed Connections

SourceSink
JCLKO_DCC_DCC0→ G:JHPFE0_CMUX_CORE_CMUX0
JCLKO_DCC_DCC0→ G:JHPFE0_CMUX_CORE_CMUX1
JCLKO_DCC_DCC0→ G:JHPFE0_DCSMUX_CORE_DCSMUX0
JCLKO_DCC_DCC0→ G:JHPFE0_DCSMUX_CORE_DCSMUX1
JCLKO_DCC_DCC10→ G:JHPFE10_CMUX_CORE_CMUX0
JCLKO_DCC_DCC10→ G:JHPFE10_CMUX_CORE_CMUX1
JCLKO_DCC_DCC10→ G:JHPFE10_DCSMUX_CORE_DCSMUX0
JCLKO_DCC_DCC10→ G:JHPFE10_DCSMUX_CORE_DCSMUX1
JCLKO_DCC_DCC11→ G:JHPFE11_CMUX_CORE_CMUX0
JCLKO_DCC_DCC11→ G:JHPFE11_CMUX_CORE_CMUX1
JCLKO_DCC_DCC11→ G:JHPFE11_DCSMUX_CORE_DCSMUX0
JCLKO_DCC_DCC11→ G:JHPFE11_DCSMUX_CORE_DCSMUX1
JCLKO_DCC_DCC1→ G:JHPFE1_CMUX_CORE_CMUX0
JCLKO_DCC_DCC1→ G:JHPFE1_CMUX_CORE_CMUX1
JCLKO_DCC_DCC1→ G:JHPFE1_DCSMUX_CORE_DCSMUX0
JCLKO_DCC_DCC1→ G:JHPFE1_DCSMUX_CORE_DCSMUX1
JCLKO_DCC_DCC2→ G:JHPFE2_CMUX_CORE_CMUX0
JCLKO_DCC_DCC2→ G:JHPFE2_CMUX_CORE_CMUX1
JCLKO_DCC_DCC2→ G:JHPFE2_DCSMUX_CORE_DCSMUX0
JCLKO_DCC_DCC2→ G:JHPFE2_DCSMUX_CORE_DCSMUX1
JCLKO_DCC_DCC3→ G:JHPFE3_CMUX_CORE_CMUX0
JCLKO_DCC_DCC3→ G:JHPFE3_CMUX_CORE_CMUX1
JCLKO_DCC_DCC3→ G:JHPFE3_DCSMUX_CORE_DCSMUX0
JCLKO_DCC_DCC3→ G:JHPFE3_DCSMUX_CORE_DCSMUX1
JCLKO_DCC_DCC4→ G:JHPFE4_CMUX_CORE_CMUX0
JCLKO_DCC_DCC4→ G:JHPFE4_CMUX_CORE_CMUX1
JCLKO_DCC_DCC4→ G:JHPFE4_DCSMUX_CORE_DCSMUX0
JCLKO_DCC_DCC4→ G:JHPFE4_DCSMUX_CORE_DCSMUX1
JCLKO_DCC_DCC5→ G:JHPFE5_CMUX_CORE_CMUX0
JCLKO_DCC_DCC5→ G:JHPFE5_CMUX_CORE_CMUX1
JCLKO_DCC_DCC5→ G:JHPFE5_DCSMUX_CORE_DCSMUX0
JCLKO_DCC_DCC5→ G:JHPFE5_DCSMUX_CORE_DCSMUX1
JCLKO_DCC_DCC6→ G:JHPFE6_CMUX_CORE_CMUX0
JCLKO_DCC_DCC6→ G:JHPFE6_CMUX_CORE_CMUX1
JCLKO_DCC_DCC6→ G:JHPFE6_DCSMUX_CORE_DCSMUX0
JCLKO_DCC_DCC6→ G:JHPFE6_DCSMUX_CORE_DCSMUX1
JCLKO_DCC_DCC7→ G:JHPFE7_CMUX_CORE_CMUX0
JCLKO_DCC_DCC7→ G:JHPFE7_CMUX_CORE_CMUX1
JCLKO_DCC_DCC7→ G:JHPFE7_DCSMUX_CORE_DCSMUX0
JCLKO_DCC_DCC7→ G:JHPFE7_DCSMUX_CORE_DCSMUX1
JCLKO_DCC_DCC8→ G:JHPFE8_CMUX_CORE_CMUX0
JCLKO_DCC_DCC8→ G:JHPFE8_CMUX_CORE_CMUX1
JCLKO_DCC_DCC8→ G:JHPFE8_DCSMUX_CORE_DCSMUX0
JCLKO_DCC_DCC8→ G:JHPFE8_DCSMUX_CORE_DCSMUX1
JCLKO_DCC_DCC9→ G:JHPFE9_CMUX_CORE_CMUX0
JCLKO_DCC_DCC9→ G:JHPFE9_CMUX_CORE_CMUX1
JCLKO_DCC_DCC9→ G:JHPFE9_DCSMUX_CORE_DCSMUX0
JCLKO_DCC_DCC9→ G:JHPFE9_DCSMUX_CORE_DCSMUX1
N2E1:JCIBMUXOUTD4→ G:JPCLKCIBL0_LMID_CORE_LMIDMUX
N1E1:JCIBMUXOUTD5→ G:JPCLKCIBL1_LMID_CORE_LMIDMUX
S1E1:JCIBMUXOUTD6→ G:JPCLKCIBL2_LMID_CORE_LMIDMUX
S2E1:JCIBMUXOUTD7→ G:JPCLKCIBL3_LMID_CORE_LMIDMUX
E13:JCIBMUXOUTD5→ G:JPCLKCIBL4_LMID_CORE_LMIDMUX
E13:JCIBMUXOUTD6→ G:JPCLKCIBL5_LMID_CORE_LMIDMUX
S9E13:JCIBMUXOUTD5→ G:JPCLKCIBL6_LMID_CORE_LMIDMUX
S9E13:JCIBMUXOUTD6→ G:JPCLKCIBL7_LMID_CORE_LMIDMUX
E25:JCIBMUXOUTD7→ G:JPCLKCIBL8_LMID_CORE_LMIDMUX
S9E25:JCIBMUXOUTD7→ G:JPCLKCIBL9_LMID_CORE_LMIDMUX
E1:JCIBMUXOUTA4→ G:JTESTINP0_LMID_CORE_LMIDMUX
E1:JCIBMUXOUTA5→ G:JTESTINP1_LMID_CORE_LMIDMUX
E1:JCIBMUXOUTA6→ G:JTESTINP2_LMID_CORE_LMIDMUX
E1:JCIBMUXOUTA7→ G:JTESTINP3_LMID_CORE_LMIDMUX
E1:JCIBMUXOUTC0→ JCE_DCC_DCC0
E1:JCIBMUXOUTC1→ JCE_DCC_DCC1
E1:JCIBMUXOUTD2→ JCE_DCC_DCC10
E1:JCIBMUXOUTD3→ JCE_DCC_DCC11
E1:JCIBMUXOUTC2→ JCE_DCC_DCC2
E1:JCIBMUXOUTC3→ JCE_DCC_DCC3
E1:JCIBMUXOUTC4→ JCE_DCC_DCC4
E1:JCIBMUXOUTC5→ JCE_DCC_DCC5
E1:JCIBMUXOUTC6→ JCE_DCC_DCC6
E1:JCIBMUXOUTC7→ JCE_DCC_DCC7
E1:JCIBMUXOUTD0→ JCE_DCC_DCC8
E1:JCIBMUXOUTD1→ JCE_DCC_DCC9
G:JHPFE0_LMID_CORE_LMIDMUX→ JCLKI_DCC_DCC0
G:JHPFE1_LMID_CORE_LMIDMUX→ JCLKI_DCC_DCC1
G:JHPFE10_LMID_CORE_LMIDMUX→ JCLKI_DCC_DCC10
G:JHPFE11_LMID_CORE_LMIDMUX→ JCLKI_DCC_DCC11
G:JHPFE2_LMID_CORE_LMIDMUX→ JCLKI_DCC_DCC2
G:JHPFE3_LMID_CORE_LMIDMUX→ JCLKI_DCC_DCC3
G:JHPFE4_LMID_CORE_LMIDMUX→ JCLKI_DCC_DCC4
G:JHPFE5_LMID_CORE_LMIDMUX→ JCLKI_DCC_DCC5
G:JHPFE6_LMID_CORE_LMIDMUX→ JCLKI_DCC_DCC6
G:JHPFE7_LMID_CORE_LMIDMUX→ JCLKI_DCC_DCC7
G:JHPFE8_LMID_CORE_LMIDMUX→ JCLKI_DCC_DCC8
G:JHPFE9_LMID_CORE_LMIDMUX→ JCLKI_DCC_DCC9
JCLKI_DCC_DCC0→ JCLKO_DCC_DCC0
JCLKI_DCC_DCC1→ JCLKO_DCC_DCC1
JCLKI_DCC_DCC10→ JCLKO_DCC_DCC10
JCLKI_DCC_DCC11→ JCLKO_DCC_DCC11
JCLKI_DCC_DCC2→ JCLKO_DCC_DCC2
JCLKI_DCC_DCC3→ JCLKO_DCC_DCC3
JCLKI_DCC_DCC4→ JCLKO_DCC_DCC4
JCLKI_DCC_DCC5→ JCLKO_DCC_DCC5
JCLKI_DCC_DCC6→ JCLKO_DCC_DCC6
JCLKI_DCC_DCC7→ JCLKO_DCC_DCC7
JCLKI_DCC_DCC8→ JCLKO_DCC_DCC8
JCLKI_DCC_DCC9→ JCLKO_DCC_DCC9