LMID Tile Documentation

Tile Bels

NameType
DCC_L0 DCC
DCC_L1 DCC
DCC_L2 DCC
DCC_L3 DCC
DCC_L4 DCC
DCC_L5 DCC
DCC_L6 DCC
DCC_L7 DCC
DCC_L8 DCC
DCC_L9 DCC
DCC_L10 DCC
DCC_L11 DCC

Config Bitmap

 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
D
D
D
D
D
D
D
D
D
D
D
D
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

Routing Muxes

Mux driving G:JHPFE0_LMID_CORE_LMIDMUX

Source F3B2 F4B2 F5B2 F6B2
G:JPCLKCIBL4_LMID_CORE_LMIDMUX 0 1 0 0
G:JPCLKT72_LMID_CORE_LMIDMUX 0 1 0 1
G:JPCLKCIBL0_LMID_CORE_LMIDMUX 0 1 1 0
G:JPCLKT61_LMID_CORE_LMIDMUX 0 1 1 1
G:JSGMIICLK0_LMID_CORE_LMIDMUX 1 0 1 1
G:JLLCLKOS3_LMID_CORE_LMIDMUX 1 1 0 0
G:JULCLKOS_LMID_CORE_LMIDMUX 1 1 0 1
G:JLLCLKOS_LMID_CORE_LMIDMUX 1 1 1 0
G:JULCLKOP_LMID_CORE_LMIDMUX 1 1 1 1

Mux driving G:JHPFE10_LMID_CORE_LMIDMUX

Source F11B4 F12B4 F13B4 F14B4
G:JPCLKCIBL8_LMID_CORE_LMIDMUX 0 1 0 0
G:JPCLKT71_LMID_CORE_LMIDMUX 0 1 0 1
G:JPCLKCIBL1_LMID_CORE_LMIDMUX 0 1 1 0
G:JPCLKT60_LMID_CORE_LMIDMUX 0 1 1 1
G:JSGMIICLK0_LMID_CORE_LMIDMUX 1 0 1 1
G:JLLCLKOS_LMID_CORE_LMIDMUX 1 1 0 0
G:JULCLKOS2_LMID_CORE_LMIDMUX 1 1 0 1
G:JLLCLKOP_LMID_CORE_LMIDMUX 1 1 1 0
G:JULCLKOP_LMID_CORE_LMIDMUX 1 1 1 1

Mux driving G:JHPFE11_LMID_CORE_LMIDMUX

Source F0B5 F1B5 F2B5 F15B4
G:JPCLKCIBL9_LMID_CORE_LMIDMUX 0 1 1 1
G:JPCLKCIBL7_LMID_CORE_LMIDMUX 1 0 0 0
G:JLLCLKOS3_LMID_CORE_LMIDMUX 1 0 0 1
G:JPCLKT71_LMID_CORE_LMIDMUX 1 0 1 0
G:JULCLKOS5_LMID_CORE_LMIDMUX 1 0 1 1
G:JPCLKCIBL3_LMID_CORE_LMIDMUX 1 1 0 0
G:JLLCLKOS_LMID_CORE_LMIDMUX 1 1 0 1
G:JPCLKT61_LMID_CORE_LMIDMUX 1 1 1 0
G:JULCLKOS4_LMID_CORE_LMIDMUX 1 1 1 1

Mux driving G:JHPFE1_LMID_CORE_LMIDMUX

Source F7B2 F8B2 F9B2 F10B2
G:JPCLKCIBL5_LMID_CORE_LMIDMUX 0 1 0 0
G:JPCLKT62_LMID_CORE_LMIDMUX 0 1 0 1
G:JPCLKCIBL1_LMID_CORE_LMIDMUX 0 1 1 0
G:JPCLKT60_LMID_CORE_LMIDMUX 0 1 1 1
G:JSGMIICLK1_LMID_CORE_LMIDMUX 1 0 0 1
G:JPCLKCIBL9_LMID_CORE_LMIDMUX 1 0 1 1
G:JLLCLKOS4_LMID_CORE_LMIDMUX 1 1 0 0
G:JULCLKOS4_LMID_CORE_LMIDMUX 1 1 0 1
G:JLLCLKOP_LMID_CORE_LMIDMUX 1 1 1 0
G:JULCLKOS_LMID_CORE_LMIDMUX 1 1 1 1

Mux driving G:JHPFE2_LMID_CORE_LMIDMUX

Source F11B2 F12B2 F13B2 F14B2
G:JPCLKCIBL6_LMID_CORE_LMIDMUX 0 1 0 0
G:JPCLKT70_LMID_CORE_LMIDMUX 0 1 0 1
G:JPCLKCIBL2_LMID_CORE_LMIDMUX 0 1 1 0
G:JPCLKT60_LMID_CORE_LMIDMUX 0 1 1 1
G:JPCLKCIBL8_LMID_CORE_LMIDMUX 1 0 1 1
G:JLLCLKOS4_LMID_CORE_LMIDMUX 1 1 0 0
G:JULCLKOS3_LMID_CORE_LMIDMUX 1 1 0 1
G:JLLCLKOS_LMID_CORE_LMIDMUX 1 1 1 0
G:JULCLKOS2_LMID_CORE_LMIDMUX 1 1 1 1

Mux driving G:JHPFE3_LMID_CORE_LMIDMUX

Source F0B3 F1B3 F2B3 F15B2
G:JSGMIICLK1_LMID_CORE_LMIDMUX 0 0 1 1
G:JPCLKCIBL9_LMID_CORE_LMIDMUX 0 1 1 1
G:JPCLKCIBL7_LMID_CORE_LMIDMUX 1 0 0 0
G:JLLCLKOS5_LMID_CORE_LMIDMUX 1 0 0 1
G:JPCLKT71_LMID_CORE_LMIDMUX 1 0 1 0
G:JULCLKOS5_LMID_CORE_LMIDMUX 1 0 1 1
G:JPCLKCIBL3_LMID_CORE_LMIDMUX 1 1 0 0
G:JLLCLKOS3_LMID_CORE_LMIDMUX 1 1 0 1
G:JPCLKT70_LMID_CORE_LMIDMUX 1 1 1 0
G:JULCLKOS4_LMID_CORE_LMIDMUX 1 1 1 1

Mux driving G:JHPFE4_LMID_CORE_LMIDMUX

Source F3B3 F4B3 F5B3 F6B3
G:JPCLKCIBL6_LMID_CORE_LMIDMUX 0 1 0 0
G:JPCLKT72_LMID_CORE_LMIDMUX 0 1 0 1
G:JPCLKCIBL4_LMID_CORE_LMIDMUX 0 1 1 0
G:JPCLKT61_LMID_CORE_LMIDMUX 0 1 1 1
G:JPCLKCIBL8_LMID_CORE_LMIDMUX 1 0 1 1
G:JLLCLKOS4_LMID_CORE_LMIDMUX 1 1 0 0
G:JULCLKOS2_LMID_CORE_LMIDMUX 1 1 0 1
G:JLLCLKOS2_LMID_CORE_LMIDMUX 1 1 1 0
G:JULCLKOS_LMID_CORE_LMIDMUX 1 1 1 1

Mux driving G:JHPFE5_LMID_CORE_LMIDMUX

Source F7B3 F8B3 F9B3 F10B3
G:JPCLKCIBL7_LMID_CORE_LMIDMUX 0 1 0 0
G:JPCLKT71_LMID_CORE_LMIDMUX 0 1 0 1
G:JPCLKCIBL2_LMID_CORE_LMIDMUX 0 1 1 0
G:JPCLKT60_LMID_CORE_LMIDMUX 0 1 1 1
G:JSGMIICLK0_LMID_CORE_LMIDMUX 1 0 1 1
G:JLLCLKOS3_LMID_CORE_LMIDMUX 1 1 0 0
G:JULCLKOS2_LMID_CORE_LMIDMUX 1 1 0 1
G:JLLCLKOP_LMID_CORE_LMIDMUX 1 1 1 0
G:JULCLKOP_LMID_CORE_LMIDMUX 1 1 1 1

Mux driving G:JHPFE6_LMID_CORE_LMIDMUX

Source F11B3 F12B3 F13B3 F14B3
G:JPCLKCIBL5_LMID_CORE_LMIDMUX 0 1 0 0
G:JPCLKT72_LMID_CORE_LMIDMUX 0 1 0 1
G:JPCLKCIBL3_LMID_CORE_LMIDMUX 0 1 1 0
G:JPCLKT70_LMID_CORE_LMIDMUX 0 1 1 1
G:JSGMIICLK1_LMID_CORE_LMIDMUX 1 0 0 1
G:JPCLKCIBL8_LMID_CORE_LMIDMUX 1 0 1 1
G:JLLCLKOS5_LMID_CORE_LMIDMUX 1 1 0 0
G:JULCLKOS5_LMID_CORE_LMIDMUX 1 1 0 1
G:JLLCLKOS2_LMID_CORE_LMIDMUX 1 1 1 0
G:JULCLKOS3_LMID_CORE_LMIDMUX 1 1 1 1

Mux driving G:JHPFE7_LMID_CORE_LMIDMUX

Source F0B4 F1B4 F2B4 F15B3
G:JPCLKCIBL5_LMID_CORE_LMIDMUX 0 1 1 1
G:JPCLKCIBL2_LMID_CORE_LMIDMUX 1 0 0 0
G:JLLCLKOS5_LMID_CORE_LMIDMUX 1 0 0 1
G:JPCLKT62_LMID_CORE_LMIDMUX 1 0 1 0
G:JULCLKOS3_LMID_CORE_LMIDMUX 1 0 1 1
G:JPCLKCIBL0_LMID_CORE_LMIDMUX 1 1 0 0
G:JLLCLKOP_LMID_CORE_LMIDMUX 1 1 0 1
G:JPCLKT61_LMID_CORE_LMIDMUX 1 1 1 0
G:JULCLKOP_LMID_CORE_LMIDMUX 1 1 1 1

Mux driving G:JHPFE8_LMID_CORE_LMIDMUX

Source F3B4 F4B4 F5B4 F6B4
G:JPCLKCIBL4_LMID_CORE_LMIDMUX 0 1 0 0
G:JPCLKT70_LMID_CORE_LMIDMUX 0 1 0 1
G:JPCLKCIBL0_LMID_CORE_LMIDMUX 0 1 1 0
G:JPCLKT62_LMID_CORE_LMIDMUX 0 1 1 1
G:JSGMIICLK1_LMID_CORE_LMIDMUX 1 0 0 1
G:JPCLKCIBL9_LMID_CORE_LMIDMUX 1 0 1 1
G:JLLCLKOS4_LMID_CORE_LMIDMUX 1 1 0 0
G:JULCLKOS4_LMID_CORE_LMIDMUX 1 1 0 1
G:JLLCLKOS2_LMID_CORE_LMIDMUX 1 1 1 0
G:JULCLKOS_LMID_CORE_LMIDMUX 1 1 1 1

Mux driving G:JHPFE9_LMID_CORE_LMIDMUX

Source F7B4 F8B4 F9B4 F10B4
G:JPCLKCIBL6_LMID_CORE_LMIDMUX 0 1 0 0
G:JPCLKT72_LMID_CORE_LMIDMUX 0 1 0 1
G:JPCLKCIBL1_LMID_CORE_LMIDMUX 0 1 1 0
G:JPCLKT62_LMID_CORE_LMIDMUX 0 1 1 1
G:JSGMIICLK0_LMID_CORE_LMIDMUX 1 0 1 1
G:JLLCLKOS5_LMID_CORE_LMIDMUX 1 1 0 0
G:JULCLKOS5_LMID_CORE_LMIDMUX 1 1 0 1
G:JLLCLKOS2_LMID_CORE_LMIDMUX 1 1 1 0
G:JULCLKOS3_LMID_CORE_LMIDMUX 1 1 1 1

Configuration Enums

Configuration enum DCC_L0.DCCEN

DCC bypassed (0) or used as gate (1)

Value F7B1
0 -
1 1

Configuration enum DCC_L1.DCCEN

DCC bypassed (0) or used as gate (1)

Value F8B1
0 -
1 1

Configuration enum DCC_L10.DCCEN

DCC bypassed (0) or used as gate (1)

Value F1B2
0 -
1 1

Configuration enum DCC_L11.DCCEN

DCC bypassed (0) or used as gate (1)

Value F2B2
0 -
1 1

Configuration enum DCC_L2.DCCEN

DCC bypassed (0) or used as gate (1)

Value F9B1
0 -
1 1

Configuration enum DCC_L3.DCCEN

DCC bypassed (0) or used as gate (1)

Value F10B1
0 -
1 1

Configuration enum DCC_L4.DCCEN

DCC bypassed (0) or used as gate (1)

Value F11B1
0 -
1 1

Configuration enum DCC_L5.DCCEN

DCC bypassed (0) or used as gate (1)

Value F12B1
0 -
1 1

Configuration enum DCC_L6.DCCEN

DCC bypassed (0) or used as gate (1)

Value F13B1
0 -
1 1

Configuration enum DCC_L7.DCCEN

DCC bypassed (0) or used as gate (1)

Value F14B1
0 -
1 1

Configuration enum DCC_L8.DCCEN

DCC bypassed (0) or used as gate (1)

Value F15B1
0 -
1 1

Configuration enum DCC_L9.DCCEN

DCC bypassed (0) or used as gate (1)

Value F0B2
0 -
1 1

Fixed Connections

SourceSink
JCLKO_DCC_DCC0→ G:JHPFE0_CMUX_CORE_CMUX0
JCLKO_DCC_DCC0→ G:JHPFE0_CMUX_CORE_CMUX1
JCLKO_DCC_DCC0→ G:JHPFE0_DCSMUX_CORE_DCSMUX0
JCLKO_DCC_DCC0→ G:JHPFE0_DCSMUX_CORE_DCSMUX1
JCLKO_DCC_DCC10→ G:JHPFE10_CMUX_CORE_CMUX0
JCLKO_DCC_DCC10→ G:JHPFE10_CMUX_CORE_CMUX1
JCLKO_DCC_DCC10→ G:JHPFE10_DCSMUX_CORE_DCSMUX0
JCLKO_DCC_DCC10→ G:JHPFE10_DCSMUX_CORE_DCSMUX1
JCLKO_DCC_DCC11→ G:JHPFE11_CMUX_CORE_CMUX0
JCLKO_DCC_DCC11→ G:JHPFE11_CMUX_CORE_CMUX1
JCLKO_DCC_DCC11→ G:JHPFE11_DCSMUX_CORE_DCSMUX0
JCLKO_DCC_DCC11→ G:JHPFE11_DCSMUX_CORE_DCSMUX1
JCLKO_DCC_DCC1→ G:JHPFE1_CMUX_CORE_CMUX0
JCLKO_DCC_DCC1→ G:JHPFE1_CMUX_CORE_CMUX1
JCLKO_DCC_DCC1→ G:JHPFE1_DCSMUX_CORE_DCSMUX0
JCLKO_DCC_DCC1→ G:JHPFE1_DCSMUX_CORE_DCSMUX1
JCLKO_DCC_DCC2→ G:JHPFE2_CMUX_CORE_CMUX0
JCLKO_DCC_DCC2→ G:JHPFE2_CMUX_CORE_CMUX1
JCLKO_DCC_DCC2→ G:JHPFE2_DCSMUX_CORE_DCSMUX0
JCLKO_DCC_DCC2→ G:JHPFE2_DCSMUX_CORE_DCSMUX1
JCLKO_DCC_DCC3→ G:JHPFE3_CMUX_CORE_CMUX0
JCLKO_DCC_DCC3→ G:JHPFE3_CMUX_CORE_CMUX1
JCLKO_DCC_DCC3→ G:JHPFE3_DCSMUX_CORE_DCSMUX0
JCLKO_DCC_DCC3→ G:JHPFE3_DCSMUX_CORE_DCSMUX1
JCLKO_DCC_DCC4→ G:JHPFE4_CMUX_CORE_CMUX0
JCLKO_DCC_DCC4→ G:JHPFE4_CMUX_CORE_CMUX1
JCLKO_DCC_DCC4→ G:JHPFE4_DCSMUX_CORE_DCSMUX0
JCLKO_DCC_DCC4→ G:JHPFE4_DCSMUX_CORE_DCSMUX1
JCLKO_DCC_DCC5→ G:JHPFE5_CMUX_CORE_CMUX0
JCLKO_DCC_DCC5→ G:JHPFE5_CMUX_CORE_CMUX1
JCLKO_DCC_DCC5→ G:JHPFE5_DCSMUX_CORE_DCSMUX0
JCLKO_DCC_DCC5→ G:JHPFE5_DCSMUX_CORE_DCSMUX1
JCLKO_DCC_DCC6→ G:JHPFE6_CMUX_CORE_CMUX0
JCLKO_DCC_DCC6→ G:JHPFE6_CMUX_CORE_CMUX1
JCLKO_DCC_DCC6→ G:JHPFE6_DCSMUX_CORE_DCSMUX0
JCLKO_DCC_DCC6→ G:JHPFE6_DCSMUX_CORE_DCSMUX1
JCLKO_DCC_DCC7→ G:JHPFE7_CMUX_CORE_CMUX0
JCLKO_DCC_DCC7→ G:JHPFE7_CMUX_CORE_CMUX1
JCLKO_DCC_DCC7→ G:JHPFE7_DCSMUX_CORE_DCSMUX0
JCLKO_DCC_DCC7→ G:JHPFE7_DCSMUX_CORE_DCSMUX1
JCLKO_DCC_DCC8→ G:JHPFE8_CMUX_CORE_CMUX0
JCLKO_DCC_DCC8→ G:JHPFE8_CMUX_CORE_CMUX1
JCLKO_DCC_DCC8→ G:JHPFE8_DCSMUX_CORE_DCSMUX0
JCLKO_DCC_DCC8→ G:JHPFE8_DCSMUX_CORE_DCSMUX1
JCLKO_DCC_DCC9→ G:JHPFE9_CMUX_CORE_CMUX0
JCLKO_DCC_DCC9→ G:JHPFE9_CMUX_CORE_CMUX1
JCLKO_DCC_DCC9→ G:JHPFE9_DCSMUX_CORE_DCSMUX0
JCLKO_DCC_DCC9→ G:JHPFE9_DCSMUX_CORE_DCSMUX1
N2E1:JCIBMUXOUTD7→ G:JPCLKCIBL0_LMID_CORE_LMIDMUX
N1E1:JCIBMUXOUTD7→ G:JPCLKCIBL1_LMID_CORE_LMIDMUX
S1E1:JCIBMUXOUTD7→ G:JPCLKCIBL2_LMID_CORE_LMIDMUX
S2E1:JCIBMUXOUTD7→ G:JPCLKCIBL3_LMID_CORE_LMIDMUX
N18E13:JCIBMUXOUTD7→ G:JPCLKCIBL4_LMID_CORE_LMIDMUX
N9E13:JCIBMUXOUTD7→ G:JPCLKCIBL5_LMID_CORE_LMIDMUX
S9E13:JCIBMUXOUTD7→ G:JPCLKCIBL6_LMID_CORE_LMIDMUX
S18E13:JCIBMUXOUTD7→ G:JPCLKCIBL7_LMID_CORE_LMIDMUX
N9E13:JCIBMUXOUTD6→ G:JPCLKCIBL8_LMID_CORE_LMIDMUX
S9E13:JCIBMUXOUTD6→ G:JPCLKCIBL9_LMID_CORE_LMIDMUX
S3E1:JCLKOUT_DLLDEL_CORE_I0→ G:JPCLKT60_LMID_CORE_LMIDMUX
S4:JINCK_SIOLOGIC_CORE_IBASE_PIC_A→ G:JPCLKT61_LMID_CORE_LMIDMUX
S4:JPADDI_SEIO33_CORE_IOA→ G:JPCLKT61_LMID_CORE_LMIDMUX
S6:JINCK_SIOLOGIC_CORE_IBASE_PIC_A→ G:JPCLKT62_LMID_CORE_LMIDMUX
S6:JPADDI_SEIO33_CORE_IOA→ G:JPCLKT62_LMID_CORE_LMIDMUX
N7E1:JCLKOUT_DLLDEL_CORE_I0→ G:JPCLKT70_LMID_CORE_LMIDMUX
N9:JINCK_SIOLOGIC_CORE_IBASE_PIC_A→ G:JPCLKT71_LMID_CORE_LMIDMUX
N9:JPADDI_SEIO33_CORE_IOA→ G:JPCLKT71_LMID_CORE_LMIDMUX
N11:JINCK_SIOLOGIC_CORE_IBASE_PIC_A→ G:JPCLKT72_LMID_CORE_LMIDMUX
N11:JPADDI_SEIO33_CORE_IOA→ G:JPCLKT72_LMID_CORE_LMIDMUX
E1:JCIBMUXOUTA4→ G:JTESTINP0_LMID_CORE_LMIDMUX
E1:JCIBMUXOUTA5→ G:JTESTINP1_LMID_CORE_LMIDMUX
E1:JCIBMUXOUTA6→ G:JTESTINP2_LMID_CORE_LMIDMUX
E1:JCIBMUXOUTA7→ G:JTESTINP3_LMID_CORE_LMIDMUX
E1:JCIBMUXOUTC0→ JCE_DCC_DCC0
E1:JCIBMUXOUTC1→ JCE_DCC_DCC1
E1:JCIBMUXOUTD2→ JCE_DCC_DCC10
E1:JCIBMUXOUTD3→ JCE_DCC_DCC11
E1:JCIBMUXOUTC2→ JCE_DCC_DCC2
E1:JCIBMUXOUTC3→ JCE_DCC_DCC3
E1:JCIBMUXOUTC4→ JCE_DCC_DCC4
E1:JCIBMUXOUTC5→ JCE_DCC_DCC5
E1:JCIBMUXOUTC6→ JCE_DCC_DCC6
E1:JCIBMUXOUTC7→ JCE_DCC_DCC7
E1:JCIBMUXOUTD0→ JCE_DCC_DCC8
E1:JCIBMUXOUTD1→ JCE_DCC_DCC9
G:JHPFE0_LMID_CORE_LMIDMUX→ JCLKI_DCC_DCC0
G:JHPFE1_LMID_CORE_LMIDMUX→ JCLKI_DCC_DCC1
G:JHPFE10_LMID_CORE_LMIDMUX→ JCLKI_DCC_DCC10
G:JHPFE11_LMID_CORE_LMIDMUX→ JCLKI_DCC_DCC11
G:JHPFE2_LMID_CORE_LMIDMUX→ JCLKI_DCC_DCC2
G:JHPFE3_LMID_CORE_LMIDMUX→ JCLKI_DCC_DCC3
G:JHPFE4_LMID_CORE_LMIDMUX→ JCLKI_DCC_DCC4
G:JHPFE5_LMID_CORE_LMIDMUX→ JCLKI_DCC_DCC5
G:JHPFE6_LMID_CORE_LMIDMUX→ JCLKI_DCC_DCC6
G:JHPFE7_LMID_CORE_LMIDMUX→ JCLKI_DCC_DCC7
G:JHPFE8_LMID_CORE_LMIDMUX→ JCLKI_DCC_DCC8
G:JHPFE9_LMID_CORE_LMIDMUX→ JCLKI_DCC_DCC9
JCLKI_DCC_DCC0→ JCLKO_DCC_DCC0
JCLKI_DCC_DCC1→ JCLKO_DCC_DCC1
JCLKI_DCC_DCC10→ JCLKO_DCC_DCC10
JCLKI_DCC_DCC11→ JCLKO_DCC_DCC11
JCLKI_DCC_DCC2→ JCLKO_DCC_DCC2
JCLKI_DCC_DCC3→ JCLKO_DCC_DCC3
JCLKI_DCC_DCC4→ JCLKO_DCC_DCC4
JCLKI_DCC_DCC5→ JCLKO_DCC_DCC5
JCLKI_DCC_DCC6→ JCLKO_DCC_DCC6
JCLKI_DCC_DCC7→ JCLKO_DCC_DCC7
JCLKI_DCC_DCC8→ JCLKO_DCC_DCC8
JCLKI_DCC_DCC9→ JCLKO_DCC_DCC9