GPLL_ULC Tile Documentation

Tile Bels

NameType
PLL_ULC PLL_CORE

Config Bitmap

 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
F
F
F
 
 
R
R
R
 
 
R
R
R
 
 
F
F
F
F
 
M
 
R
 
L
 
 
 
 
 
 
 
 
 
 
 
L
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

Routing Muxes

Mux driving S1:JFBKCK_FBMUX_CORE_I_FBKMUX

Source F35B0 F36B0 F37B0 F38B0
S1:JFBKCLK0_FBMUX_CORE_I_FBKMUX - - - -
S1:JFBKCLK8_FBMUX_CORE_I_FBKMUX - - - 1
S1:JFBKCLK4_FBMUX_CORE_I_FBKMUX - - 1 -
S1:JFBKCLK12_FBMUX_CORE_I_FBKMUX - - 1 1
S1:JFBKCLK2_FBMUX_CORE_I_FBKMUX - 1 - -
S1:JFBKCLK10_FBMUX_CORE_I_FBKMUX - 1 - 1
S1:JFBKCLK6_FBMUX_CORE_I_FBKMUX - 1 1 -
S1:JFBKCLK14_FBMUX_CORE_I_FBKMUX - 1 1 1
S1:JFBKCLK1_FBMUX_CORE_I_FBKMUX 1 - - -
S1:JFBKCLK9_FBMUX_CORE_I_FBKMUX 1 - - 1
S1:JFBKCLK5_FBMUX_CORE_I_FBKMUX 1 - 1 -
S1:JFBKCLK13_FBMUX_CORE_I_FBKMUX 1 - 1 1
S1:JFBKCLK3_FBMUX_CORE_I_FBKMUX 1 1 - -
S1:JFBKCLK11_FBMUX_CORE_I_FBKMUX 1 1 - 1
S1:JFBKCLK7_FBMUX_CORE_I_FBKMUX 1 1 1 -
S1:JFBKCLK15_FBMUX_CORE_I_FBKMUX 1 1 1 1

Mux driving S1:JREFCK_REFMUX_CORE_I_REFMUX

Source F25B0 F26B0 F27B0 F30B0 F31B0 F32B0 F42B0
S1:JREFCLK10_REFMUX_CORE_I_REFMUX - - - - - - -
S1:JREFCLK20_REFMUX_CORE_I_REFMUX - - - - - - 1
S1:JREFCLK24_REFMUX_CORE_I_REFMUX - - - - - 1 1
S1:JREFCLK22_REFMUX_CORE_I_REFMUX - - - - 1 - 1
S1:JREFCLK26_REFMUX_CORE_I_REFMUX - - - - 1 1 1
S1:JREFCLK21_REFMUX_CORE_I_REFMUX - - - 1 - - 1
S1:JREFCLK25_REFMUX_CORE_I_REFMUX - - - 1 - 1 1
S1:JREFCLK23_REFMUX_CORE_I_REFMUX - - - 1 1 - 1
S1:JREFCLK27_REFMUX_CORE_I_REFMUX - - - 1 1 1 1
S1:JREFCLK14_REFMUX_CORE_I_REFMUX - - 1 - - - -
S1:JREFCLK12_REFMUX_CORE_I_REFMUX - 1 - - - - -
S1:JREFCLK16_REFMUX_CORE_I_REFMUX - 1 1 - - - -
S1:JREFCLK11_REFMUX_CORE_I_REFMUX 1 - - - - - -
S1:JREFCLK15_REFMUX_CORE_I_REFMUX 1 - 1 - - - -
S1:JREFCLK13_REFMUX_CORE_I_REFMUX 1 1 - - - - -
S1:JREFCLK17_REFMUX_CORE_I_REFMUX 1 1 1 - - - -

Configuration Enums

Configuration enum PLL_ULC.CLKMUX_FB

internal feedback selection

Value F20B0 F21B0 F22B0
CMUX_CLKOP - - -
CMUX_CLKOS 1 - -
CMUX_CLKOS2 - 1 -
CMUX_CLKOS3 1 1 -
CMUX_CLKOS4 - - 1
CMUX_CLKOS5 1 - 1

Configuration enum PLL_ULC.LMMICLKMUX

Value F44B0
INV 1
LMMICLK -

Configuration enum PLL_ULC.LMMIRESETNMUX

Value F56B0
INV 1
LMMIRESETN -

Configuration enum PLL_ULC.MODE

PLL_CORE primitive mode

Value F40B0
NONE -
PLL_CORE 1

Fixed Connections

SourceSink
S1:JCLKOP_PLL_CORE_I_PLL_LMMI G:JULCLKOP_LMID_CORE_LMIDMUX
S1:JCLKOP_PLL_CORE_I_PLL_LMMI G:JULCLKOP_TMID_CORE_TMIDMUX
S1:JCLKOS2_PLL_CORE_I_PLL_LMMI G:JULCLKOS2_LMID_CORE_LMIDMUX
S1:JCLKOS2_PLL_CORE_I_PLL_LMMI G:JULCLKOS2_TMID_CORE_TMIDMUX
S1:JCLKOS3_PLL_CORE_I_PLL_LMMI G:JULCLKOS3_LMID_CORE_LMIDMUX
S1:JCLKOS3_PLL_CORE_I_PLL_LMMI G:JULCLKOS3_TMID_CORE_TMIDMUX
S1:JCLKOS4_PLL_CORE_I_PLL_LMMI G:JULCLKOS4_LMID_CORE_LMIDMUX
S1:JCLKOS5_PLL_CORE_I_PLL_LMMI G:JULCLKOS5_LMID_CORE_LMIDMUX
S1:JCLKOS_PLL_CORE_I_PLL_LMMI G:JULCLKOS_LMID_CORE_LMIDMUX
S1:JCLKOS_PLL_CORE_I_PLL_LMMI G:JULCLKOS_TMID_CORE_TMIDMUX
S2:JCIBMUXOUTB0 S1:JBINACT0_PLL_CORE_I_PLL_LMMI
S2:JCIBMUXOUTB1 S1:JBINACT1_PLL_CORE_I_PLL_LMMI
S2:JCIBMUXOUTB2 S1:JBINTEST0_PLL_CORE_I_PLL_LMMI
S2:JCIBMUXOUTB3 S1:JBINTEST1_PLL_CORE_I_PLL_LMMI
S1:JCIBMUXOUTC4 S1:JCIBDIR_PLL_CORE_I_PLL_LMMI
S1:JCIBMUXOUTC2 S1:JCIBDSEL0_PLL_CORE_I_PLL_LMMI
S1:JCIBMUXOUTC1 S1:JCIBDSEL1_PLL_CORE_I_PLL_LMMI
S1:JCIBMUXOUTC0 S1:JCIBDSEL2_PLL_CORE_I_PLL_LMMI
S1:JCIBMUXOUTB3 S1:JCIBLDREG_PLL_CORE_I_PLL_LMMI
S1:JCIBMUXOUTC3 S1:JCIBROT_PLL_CORE_I_PLL_LMMI
S2:JCIBMUXOUTB5 S1:JDIRDELP1_PLL_CORE_I_PLL_LMMI
S2:JCIBMUXOUTB4 S1:JDIRDEL_PLL_CORE_I_PLL_LMMI
S1:JCIBMUXOUTA0 S1:JENCLKOP_PLL_CORE_I_PLL_LMMI
S1:JCIBMUXOUTA2 S1:JENCLKOS2_PLL_CORE_I_PLL_LMMI
S1:JCIBMUXOUTA3 S1:JENCLKOS3_PLL_CORE_I_PLL_LMMI
S1:JCIBMUXOUTA4 S1:JENCLKOS4_PLL_CORE_I_PLL_LMMI
S1:JCIBMUXOUTA5 S1:JENCLKOS5_PLL_CORE_I_PLL_LMMI
S1:JCIBMUXOUTA1 S1:JENCLKOS_PLL_CORE_I_PLL_LMMI
S1:JENEXT_FBMUX_CORE_I_FBKMUX S1:JENEXT_PLL_CORE_I_PLL_LMMI
S1:JREFMUXCK_PLL_CORE_I_PLL_LMMI S1:JF0
S1:JLOCK_PLL_CORE_I_PLL_LMMI S1:JF1
S1:JINTLOCK_PLL_CORE_I_PLL_LMMI S1:JF2
S1:JPFDUP_PLL_CORE_I_PLL_LMMI S1:JF3
S1:JPFDDN_PLL_CORE_I_PLL_LMMI S1:JF4
S1:JLMMIRDATA0_PLL_CORE_I_PLL_LMMI S1:JF5
S1:JLMMIRDATA1_PLL_CORE_I_PLL_LMMI S1:JF6
S1:JLMMIRDATA2_PLL_CORE_I_PLL_LMMI S1:JF7
S1:JFBKCK_FBMUX_CORE_I_FBKMUX S1:JFBKCK_PLL_CORE_I_PLL_LMMI
S1:JINTFBK0_PLL_CORE_I_PLL_LMMI S1:JFBKCLK0_FBMUX_CORE_I_FBKMUX
S1:JCLK1 S1:JFBKCLK11_FBMUX_CORE_I_FBKMUX
S1:JINTFBK1_PLL_CORE_I_PLL_LMMI S1:JFBKCLK1_FBMUX_CORE_I_FBKMUX
S1:JINTFBK2_PLL_CORE_I_PLL_LMMI S1:JFBKCLK2_FBMUX_CORE_I_FBKMUX
S1:JINTFBK3_PLL_CORE_I_PLL_LMMI S1:JFBKCLK3_FBMUX_CORE_I_FBKMUX
S1:JINTFBK4_PLL_CORE_I_PLL_LMMI S1:JFBKCLK4_FBMUX_CORE_I_FBKMUX
S1:JINTFBK5_PLL_CORE_I_PLL_LMMI S1:JFBKCLK5_FBMUX_CORE_I_FBKMUX
S1:JCLKOUTDL_PLL_CORE_I_PLL_LMMI S1:JFBKCLK6_FBMUX_CORE_I_FBKMUX
S2:JCIBMUXOUTC0 S1:JGRAYACT0_PLL_CORE_I_PLL_LMMI
S2:JCIBMUXOUTC1 S1:JGRAYACT1_PLL_CORE_I_PLL_LMMI
S2:JCIBMUXOUTC2 S1:JGRAYACT2_PLL_CORE_I_PLL_LMMI
S2:JCIBMUXOUTC3 S1:JGRAYACT3_PLL_CORE_I_PLL_LMMI
S2:JCIBMUXOUTA0 S1:JGRAYACT4_PLL_CORE_I_PLL_LMMI
S2:JCIBMUXOUTD3 S1:JGRAYTEST0_PLL_CORE_I_PLL_LMMI
S2:JCIBMUXOUTD4 S1:JGRAYTEST1_PLL_CORE_I_PLL_LMMI
S2:JCIBMUXOUTD5 S1:JGRAYTEST2_PLL_CORE_I_PLL_LMMI
S2:JCIBMUXOUTD6 S1:JGRAYTEST3_PLL_CORE_I_PLL_LMMI
S2:JCIBMUXOUTA2 S1:JGRAYTEST4_PLL_CORE_I_PLL_LMMI
S1:JINTLOCK_PLL_CORE_I_PLL_LMMI S1:JINTLOCK_FBMUX_CORE_I_FBKMUX
S2:JCIBMUXOUTD0 S1:JLEGACY_PLL_CORE_I_PLL_LMMI
S1:JLEGRDYN_PLL_CORE_I_PLL_LMMI S1:JLGYRDYN_FBMUX_CORE_I_FBKMUX
S2:JCLK1 S1:JLMMICLK_PLL_CORE_I_PLL_LMMI
S1:JCIBMUXOUTB4 S1:JLMMIOFFSET0_PLL_CORE_I_PLL_LMMI
S1:JCIBMUXOUTB5 S1:JLMMIOFFSET1_PLL_CORE_I_PLL_LMMI
S1:JCIBMUXOUTB6 S1:JLMMIOFFSET2_PLL_CORE_I_PLL_LMMI
S1:JCIBMUXOUTB7 S1:JLMMIOFFSET3_PLL_CORE_I_PLL_LMMI
S2:JCIBMUXOUTC4 S1:JLMMIOFFSET4_PLL_CORE_I_PLL_LMMI
S2:JCIBMUXOUTC5 S1:JLMMIOFFSET5_PLL_CORE_I_PLL_LMMI
S2:JCIBMUXOUTC6 S1:JLMMIOFFSET6_PLL_CORE_I_PLL_LMMI
S1:JCIBMUXOUTA6 S1:JLMMIREQUEST_PLL_CORE_I_PLL_LMMI
S1:JLSR0 S1:JLMMIRESETN_PLL_CORE_I_PLL_LMMI
S1:JCIBMUXOUTD2 S1:JLMMIWDATA0_PLL_CORE_I_PLL_LMMI
S1:JCIBMUXOUTD3 S1:JLMMIWDATA1_PLL_CORE_I_PLL_LMMI
S1:JCIBMUXOUTD4 S1:JLMMIWDATA2_PLL_CORE_I_PLL_LMMI
S1:JCIBMUXOUTD5 S1:JLMMIWDATA3_PLL_CORE_I_PLL_LMMI
S2:JCIBMUXOUTA4 S1:JLMMIWDATA4_PLL_CORE_I_PLL_LMMI
S2:JCIBMUXOUTA5 S1:JLMMIWDATA5_PLL_CORE_I_PLL_LMMI
S2:JCIBMUXOUTA6 S1:JLMMIWDATA6_PLL_CORE_I_PLL_LMMI
S2:JCIBMUXOUTA7 S1:JLMMIWDATA7_PLL_CORE_I_PLL_LMMI
S1:JCIBMUXOUTA7 S1:JLMMIWRRDN_PLL_CORE_I_PLL_LMMI
S1E1:JCLK0 S1:JOPCGLDCK_PLL_CORE_I_PLL_LMMI
S2:JCIBMUXOUTD2 S1:JPLLPDN_PLL_CORE_I_PLL_LMMI
S2:JLSR0 S1:JPLLRESET_PLL_CORE_I_PLL_LMMI
S1:JCLKOP_PLL_CORE_I_PLL_LMMI S1:JQ0
S1:JCLKOS_PLL_CORE_I_PLL_LMMI S1:JQ1
S1:JCLKOS2_PLL_CORE_I_PLL_LMMI S1:JQ2
S1:JCLKOS3_PLL_CORE_I_PLL_LMMI S1:JQ3
S1:JCLKOS4_PLL_CORE_I_PLL_LMMI S1:JQ4
S1:JCLKOS5_PLL_CORE_I_PLL_LMMI S1:JQ5
S1:JLMMIRDATA3_PLL_CORE_I_PLL_LMMI S1:JQ6
S1:JLMMIREADY_PLL_CORE_I_PLL_LMMI S1:JQ7
S1:JREFCK_REFMUX_CORE_I_REFMUX S1:JREFCK_PLL_CORE_I_PLL_LMMI
S1:JCLK0 S1:JREFCLK11_REFMUX_CORE_I_REFMUX
S20W1:JINCK_SIOLOGIC_CORE_IBASE_PIC_A S1:JREFCLK13_REFMUX_CORE_I_REFMUX
S20W1:JPADDI_SEIO33_CORE_IOA S1:JREFCLK13_REFMUX_CORE_I_REFMUX
S3W1:JINCK_SIOLOGIC_CORE_IBASE_PIC_A S1:JREFCLK14_REFMUX_CORE_I_REFMUX
S3W1:JPADDI_SEIO33_CORE_IOA S1:JREFCLK14_REFMUX_CORE_I_REFMUX
E75:JINCK_SIOLOGIC_CORE_IBASE_PIC_A S1:JREFCLK16_REFMUX_CORE_I_REFMUX
E75:JPADDI_SEIO33_CORE_IOA S1:JREFCLK16_REFMUX_CORE_I_REFMUX
S2:JCLK0 S1:JREFCLK21_REFMUX_CORE_I_REFMUX
S19W1:JINCK_SIOLOGIC_CORE_IBASE_PIC_A S1:JREFCLK23_REFMUX_CORE_I_REFMUX
S19W1:JPADDI_SEIO33_CORE_IOA S1:JREFCLK23_REFMUX_CORE_I_REFMUX
E77:JINCK_SIOLOGIC_CORE_IBASE_PIC_A S1:JREFCLK26_REFMUX_CORE_I_REFMUX
E77:JPADDI_SEIO33_CORE_IOA S1:JREFCLK26_REFMUX_CORE_I_REFMUX
S1:JCIBMUXOUTB0 S1:JREFSEL_REFMUX_CORE_I_REFMUX
S2:JCIBMUXOUTB7 S1:JROTDELP1_PLL_CORE_I_PLL_LMMI
S2:JCIBMUXOUTB6 S1:JROTDEL_PLL_CORE_I_PLL_LMMI
S1:JCIBMUXOUTD7 S1:JSCANCLK_PLL_CORE_I_PLL_LMMI
S2:JLSR1 S1:JSCANRST_PLL_CORE_I_PLL_LMMI
S2:JCIBMUXOUTD1 S1:JSTDBY_PLL_CORE_I_PLL_LMMI
S1:JCIBMUXOUTB2 S1:JWKUPSYNC_FBMUX_CORE_I_FBKMUX
S1:JZRSEL3_REFMUX_CORE_I_REFMUX S1:JZRSEL3_PLL_CORE_I_PLL_LMMI
S1:JLMMIRDATAVALID_PLL_CORE_I_PLL_LMMI S2:JF3
S1:JLMMIRDATA4_PLL_CORE_I_PLL_LMMI S2:JF4
S1:JLMMIRDATA5_PLL_CORE_I_PLL_LMMI S2:JF5
S1:JLMMIRDATA6_PLL_CORE_I_PLL_LMMI S2:JF6
S1:JLMMIRDATA7_PLL_CORE_I_PLL_LMMI S2:JF7
S1:JREGQA_PLL_CORE_I_PLL_LMMI S2:JQ0
S1:JREGQB_PLL_CORE_I_PLL_LMMI S2:JQ1
S1:JREGQB1_PLL_CORE_I_PLL_LMMI S2:JQ2