GPLL_LRC Tile Documentation

Tile Bels

NameType
PLL_LRC PLL_CORE

Config Bitmap

 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
R
R
 
 
R
R
R
 
 
F
F
F
 
 
 
 
 
 
 
L
 
R
 
M
 
F
F
F
F
 
 
R
 
 
 
 
 
 
 
L
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

Routing Muxes

Mux driving W1:JFBKCK_FBMUX_CORE_I_FBKMUX

Source F9B2 F10B2 F11B2 F12B2
W1:JFBKCLK0_FBMUX_CORE_I_FBKMUX - - - -
W1:JFBKCLK1_FBMUX_CORE_I_FBKMUX - - - 1
W1:JFBKCLK2_FBMUX_CORE_I_FBKMUX - - 1 -
W1:JFBKCLK3_FBMUX_CORE_I_FBKMUX - - 1 1
W1:JFBKCLK4_FBMUX_CORE_I_FBKMUX - 1 - -
W1:JFBKCLK5_FBMUX_CORE_I_FBKMUX - 1 - 1
W1:JFBKCLK6_FBMUX_CORE_I_FBKMUX - 1 1 -
W1:JFBKCLK7_FBMUX_CORE_I_FBKMUX - 1 1 1
W1:JFBKCLK8_FBMUX_CORE_I_FBKMUX 1 - - -
W1:JFBKCLK9_FBMUX_CORE_I_FBKMUX 1 - - 1
W1:JFBKCLK10_FBMUX_CORE_I_FBKMUX 1 - 1 -
W1:JFBKCLK11_FBMUX_CORE_I_FBKMUX 1 - 1 1
W1:JFBKCLK12_FBMUX_CORE_I_FBKMUX 1 1 - -
W1:JFBKCLK13_FBMUX_CORE_I_FBKMUX 1 1 - 1
W1:JFBKCLK14_FBMUX_CORE_I_FBKMUX 1 1 1 -
W1:JFBKCLK15_FBMUX_CORE_I_FBKMUX 1 1 1 1

Mux driving W1:JREFCK_REFMUX_CORE_I_REFMUX

Source F0B1 F1B1 F4B1 F5B1 F5B2 F6B1 F15B2
W1:JREFCLK10_REFMUX_CORE_I_REFMUX - - - - - - -
W1:JREFCLK11_REFMUX_CORE_I_REFMUX - - - - - 1 -
W1:JREFCLK20_REFMUX_CORE_I_REFMUX - - - - 1 - -
W1:JREFCLK24_REFMUX_CORE_I_REFMUX - - - - 1 - 1
W1:JREFCLK12_REFMUX_CORE_I_REFMUX - - - 1 - - -
W1:JREFCLK13_REFMUX_CORE_I_REFMUX - - - 1 - 1 -
W1:JREFCLK14_REFMUX_CORE_I_REFMUX - - 1 - - - -
W1:JREFCLK15_REFMUX_CORE_I_REFMUX - - 1 - - 1 -
W1:JREFCLK16_REFMUX_CORE_I_REFMUX - - 1 1 - - -
W1:JREFCLK17_REFMUX_CORE_I_REFMUX - - 1 1 - 1 -
W1:JREFCLK21_REFMUX_CORE_I_REFMUX - 1 - - 1 - -
W1:JREFCLK25_REFMUX_CORE_I_REFMUX - 1 - - 1 - 1
W1:JREFCLK22_REFMUX_CORE_I_REFMUX 1 - - - 1 - -
W1:JREFCLK26_REFMUX_CORE_I_REFMUX 1 - - - 1 - 1
W1:JREFCLK23_REFMUX_CORE_I_REFMUX 1 1 - - 1 - -
W1:JREFCLK27_REFMUX_CORE_I_REFMUX 1 1 - - 1 - 1

Configuration Enums

Configuration enum PLL_LRC.CLKMUX_FB

internal feedback selection

Value F9B1 F10B1 F11B1
CMUX_CLKOP - - -
CMUX_CLKOS - - 1
CMUX_CLKOS2 - 1 -
CMUX_CLKOS3 - 1 1
CMUX_CLKOS4 1 - -
CMUX_CLKOS5 1 - 1

Configuration enum PLL_LRC.LMMICLKMUX

Value F3B2
INV 1
LMMICLK -

Configuration enum PLL_LRC.LMMIRESETNMUX

Value F7B3
INV 1
LMMIRESETN -

Configuration enum PLL_LRC.MODE

PLL_CORE primitive mode

Value F7B2
NONE -
PLL_CORE 1

Fixed Connections

SourceSink
W1:JCLKOP_PLL_CORE_I_PLL_LMMI→ G:JLRCLKOP_BMID_CORE_BMIDMUX
W1:JCLKOP_PLL_CORE_I_PLL_LMMI→ G:JLRCLKOP_RMID_CORE_RMIDMUX
W1:JCLKOS2_PLL_CORE_I_PLL_LMMI→ G:JLRCLKOS2_BMID_CORE_BMIDMUX
W1:JCLKOS2_PLL_CORE_I_PLL_LMMI→ G:JLRCLKOS2_RMID_CORE_RMIDMUX
W1:JCLKOS3_PLL_CORE_I_PLL_LMMI→ G:JLRCLKOS3_BMID_CORE_BMIDMUX
W1:JCLKOS3_PLL_CORE_I_PLL_LMMI→ G:JLRCLKOS3_RMID_CORE_RMIDMUX
W1:JCLKOS4_PLL_CORE_I_PLL_LMMI→ G:JLRCLKOS4_BMID_CORE_BMIDMUX
W1:JCLKOS4_PLL_CORE_I_PLL_LMMI→ G:JLRCLKOS4_RMID_CORE_RMIDMUX
W1:JCLKOS5_PLL_CORE_I_PLL_LMMI→ G:JLRCLKOS5_BMID_CORE_BMIDMUX
W1:JCLKOS5_PLL_CORE_I_PLL_LMMI→ G:JLRCLKOS5_RMID_CORE_RMIDMUX
W1:JCLKOS_PLL_CORE_I_PLL_LMMI→ G:JLRCLKOS_BMID_CORE_BMIDMUX
W1:JCLKOS_PLL_CORE_I_PLL_LMMI→ G:JLRCLKOS_RMID_CORE_RMIDMUX
W1:JLMMIRDATAVALID_PLL_CORE_I_PLL_LMMI→ N1W1:JF3
W1:JLMMIRDATA4_PLL_CORE_I_PLL_LMMI→ N1W1:JF4
W1:JLMMIRDATA5_PLL_CORE_I_PLL_LMMI→ N1W1:JF5
W1:JLMMIRDATA6_PLL_CORE_I_PLL_LMMI→ N1W1:JF6
W1:JLMMIRDATA7_PLL_CORE_I_PLL_LMMI→ N1W1:JF7
W1:JREGQA_PLL_CORE_I_PLL_LMMI→ N1W1:JQ0
W1:JREGQB_PLL_CORE_I_PLL_LMMI→ N1W1:JQ1
W1:JREGQB1_PLL_CORE_I_PLL_LMMI→ N1W1:JQ2
W1:JCLKOS4_PLL_CORE_I_PLL_LMMI→ N3W1:JCLKDCLK_ADC_CORE_ADC0
W1:JCLKOP_PLL_CORE_I_PLL_LMMI→ S2W36:JLRCLKOP_ECLKLOGICMUXPLLFB_CORE_ECLKPLLFBR
W1:JCLKOS2_PLL_CORE_I_PLL_LMMI→ S2W36:JLRCLKOS2_ECLKLOGICMUXPLLFB_CORE_ECLKPLLFBR
W1:JCLKOS3_PLL_CORE_I_PLL_LMMI→ S2W36:JLRCLKOS3_ECLKLOGICMUXPLLFB_CORE_ECLKPLLFBR
W1:JCLKOS4_PLL_CORE_I_PLL_LMMI→ S2W36:JLRCLKOS4_ECLKLOGICMUXPLLFB_CORE_ECLKPLLFBR
W1:JCLKOS5_PLL_CORE_I_PLL_LMMI→ S2W36:JLRCLKOS5_ECLKLOGICMUXPLLFB_CORE_ECLKPLLFBR
W1:JCLKOS_PLL_CORE_I_PLL_LMMI→ S2W36:JLRCLKOS_ECLKLOGICMUXPLLFB_CORE_ECLKPLLFBR
W1:JCLKOP_PLL_CORE_I_PLL_LMMI→ S2W37:JLRCLKOP_ECLKBANK_CORE_ECLKBANK3
W1:JCLKOS2_PLL_CORE_I_PLL_LMMI→ S2W37:JLRCLKOS2_ECLKBANK_CORE_ECLKBANK3
W1:JCLKOS3_PLL_CORE_I_PLL_LMMI→ S2W37:JLRCLKOS3_ECLKBANK_CORE_ECLKBANK3
W1:JCLKOS4_PLL_CORE_I_PLL_LMMI→ S2W37:JLRCLKOS4_ECLKBANK_CORE_ECLKBANK3
W1:JCLKOS5_PLL_CORE_I_PLL_LMMI→ S2W37:JLRCLKOS5_ECLKBANK_CORE_ECLKBANK3
W1:JCLKOS_PLL_CORE_I_PLL_LMMI→ S2W37:JLRCLKOS_ECLKBANK_CORE_ECLKBANK3
W1:JCLKOP_PLL_CORE_I_PLL_LMMI→ S2W38:JLRCLKOP_ECLKBANK_CORE_ECLKBANK4
W1:JCLKOS2_PLL_CORE_I_PLL_LMMI→ S2W38:JLRCLKOS2_ECLKBANK_CORE_ECLKBANK4
W1:JCLKOS3_PLL_CORE_I_PLL_LMMI→ S2W38:JLRCLKOS3_ECLKBANK_CORE_ECLKBANK4
W1:JCLKOS4_PLL_CORE_I_PLL_LMMI→ S2W38:JLRCLKOS4_ECLKBANK_CORE_ECLKBANK4
W1:JCLKOS5_PLL_CORE_I_PLL_LMMI→ S2W38:JLRCLKOS5_ECLKBANK_CORE_ECLKBANK4
W1:JCLKOS_PLL_CORE_I_PLL_LMMI→ S2W38:JLRCLKOS_ECLKBANK_CORE_ECLKBANK4
W1:JCLKOP_PLL_CORE_I_PLL_LMMI→ S2W39:JLRCLKOP_ECLKBANK_CORE_ECLKBANK5
W1:JCLKOS2_PLL_CORE_I_PLL_LMMI→ S2W39:JLRCLKOS2_ECLKBANK_CORE_ECLKBANK5
W1:JCLKOS3_PLL_CORE_I_PLL_LMMI→ S2W39:JLRCLKOS3_ECLKBANK_CORE_ECLKBANK5
W1:JCLKOS4_PLL_CORE_I_PLL_LMMI→ S2W39:JLRCLKOS4_ECLKBANK_CORE_ECLKBANK5
W1:JCLKOS5_PLL_CORE_I_PLL_LMMI→ S2W39:JLRCLKOS5_ECLKBANK_CORE_ECLKBANK5
W1:JCLKOS_PLL_CORE_I_PLL_LMMI→ S2W39:JLRCLKOS_ECLKBANK_CORE_ECLKBANK5
W1:JCLKOP_PLL_CORE_I_PLL_LMMI→ S2W40:JLRCLKOP_ECLKLOGICMUXPLLFB_CORE_ECLKPLLFBL
W1:JCLKOS2_PLL_CORE_I_PLL_LMMI→ S2W40:JLRCLKOS2_ECLKLOGICMUXPLLFB_CORE_ECLKPLLFBL
W1:JCLKOS3_PLL_CORE_I_PLL_LMMI→ S2W40:JLRCLKOS3_ECLKLOGICMUXPLLFB_CORE_ECLKPLLFBL
W1:JCLKOS4_PLL_CORE_I_PLL_LMMI→ S2W40:JLRCLKOS4_ECLKLOGICMUXPLLFB_CORE_ECLKPLLFBL
W1:JCLKOS5_PLL_CORE_I_PLL_LMMI→ S2W40:JLRCLKOS5_ECLKLOGICMUXPLLFB_CORE_ECLKPLLFBL
W1:JCLKOS_PLL_CORE_I_PLL_LMMI→ S2W40:JLRCLKOS_ECLKLOGICMUXPLLFB_CORE_ECLKPLLFBL
N1W1:JCIBMUXOUTB0→ W1:JBINACT0_PLL_CORE_I_PLL_LMMI
N1W1:JCIBMUXOUTB1→ W1:JBINACT1_PLL_CORE_I_PLL_LMMI
N1W1:JCIBMUXOUTB2→ W1:JBINTEST0_PLL_CORE_I_PLL_LMMI
N1W1:JCIBMUXOUTB3→ W1:JBINTEST1_PLL_CORE_I_PLL_LMMI
W1:JCIBMUXOUTC4→ W1:JCIBDIR_PLL_CORE_I_PLL_LMMI
W1:JCIBMUXOUTC2→ W1:JCIBDSEL0_PLL_CORE_I_PLL_LMMI
W1:JCIBMUXOUTC1→ W1:JCIBDSEL1_PLL_CORE_I_PLL_LMMI
W1:JCIBMUXOUTC0→ W1:JCIBDSEL2_PLL_CORE_I_PLL_LMMI
W1:JCIBMUXOUTB3→ W1:JCIBLDREG_PLL_CORE_I_PLL_LMMI
W1:JCIBMUXOUTC3→ W1:JCIBROT_PLL_CORE_I_PLL_LMMI
N1W1:JCIBMUXOUTB5→ W1:JDIRDELP1_PLL_CORE_I_PLL_LMMI
N1W1:JCIBMUXOUTB4→ W1:JDIRDEL_PLL_CORE_I_PLL_LMMI
W1:JCIBMUXOUTA0→ W1:JENCLKOP_PLL_CORE_I_PLL_LMMI
W1:JCIBMUXOUTA2→ W1:JENCLKOS2_PLL_CORE_I_PLL_LMMI
W1:JCIBMUXOUTA3→ W1:JENCLKOS3_PLL_CORE_I_PLL_LMMI
W1:JCIBMUXOUTA4→ W1:JENCLKOS4_PLL_CORE_I_PLL_LMMI
W1:JCIBMUXOUTA5→ W1:JENCLKOS5_PLL_CORE_I_PLL_LMMI
W1:JCIBMUXOUTA1→ W1:JENCLKOS_PLL_CORE_I_PLL_LMMI
W1:JENEXT_FBMUX_CORE_I_FBKMUX→ W1:JENEXT_PLL_CORE_I_PLL_LMMI
W1:JREFMUXCK_PLL_CORE_I_PLL_LMMI→ W1:JF0
W1:JLOCK_PLL_CORE_I_PLL_LMMI→ W1:JF1
W1:JINTLOCK_PLL_CORE_I_PLL_LMMI→ W1:JF2
W1:JPFDUP_PLL_CORE_I_PLL_LMMI→ W1:JF3
W1:JPFDDN_PLL_CORE_I_PLL_LMMI→ W1:JF4
W1:JLMMIRDATA0_PLL_CORE_I_PLL_LMMI→ W1:JF5
W1:JLMMIRDATA1_PLL_CORE_I_PLL_LMMI→ W1:JF6
W1:JLMMIRDATA2_PLL_CORE_I_PLL_LMMI→ W1:JF7
W1:JFBKCK_FBMUX_CORE_I_FBKMUX→ W1:JFBKCK_PLL_CORE_I_PLL_LMMI
W1:JINTFBK0_PLL_CORE_I_PLL_LMMI→ W1:JFBKCLK0_FBMUX_CORE_I_FBKMUX
S2W36:JECLKOUT_ECLKLOGICMUXPLLFB_CORE_ECLKPLLFBR→ W1:JFBKCLK10_FBMUX_CORE_I_FBKMUX
W1:JCLK1→ W1:JFBKCLK11_FBMUX_CORE_I_FBKMUX
W1:JINTFBK1_PLL_CORE_I_PLL_LMMI→ W1:JFBKCLK1_FBMUX_CORE_I_FBKMUX
W1:JINTFBK2_PLL_CORE_I_PLL_LMMI→ W1:JFBKCLK2_FBMUX_CORE_I_FBKMUX
W1:JINTFBK3_PLL_CORE_I_PLL_LMMI→ W1:JFBKCLK3_FBMUX_CORE_I_FBKMUX
W1:JINTFBK4_PLL_CORE_I_PLL_LMMI→ W1:JFBKCLK4_FBMUX_CORE_I_FBKMUX
W1:JINTFBK5_PLL_CORE_I_PLL_LMMI→ W1:JFBKCLK5_FBMUX_CORE_I_FBKMUX
W1:JCLKOUTDL_PLL_CORE_I_PLL_LMMI→ W1:JFBKCLK6_FBMUX_CORE_I_FBKMUX
N1W1:JCIBMUXOUTC0→ W1:JGRAYACT0_PLL_CORE_I_PLL_LMMI
N1W1:JCIBMUXOUTC1→ W1:JGRAYACT1_PLL_CORE_I_PLL_LMMI
N1W1:JCIBMUXOUTC2→ W1:JGRAYACT2_PLL_CORE_I_PLL_LMMI
N1W1:JCIBMUXOUTC3→ W1:JGRAYACT3_PLL_CORE_I_PLL_LMMI
N1W1:JCIBMUXOUTA0→ W1:JGRAYACT4_PLL_CORE_I_PLL_LMMI
N1W1:JCIBMUXOUTD3→ W1:JGRAYTEST0_PLL_CORE_I_PLL_LMMI
N1W1:JCIBMUXOUTD4→ W1:JGRAYTEST1_PLL_CORE_I_PLL_LMMI
N1W1:JCIBMUXOUTD5→ W1:JGRAYTEST2_PLL_CORE_I_PLL_LMMI
N1W1:JCIBMUXOUTD6→ W1:JGRAYTEST3_PLL_CORE_I_PLL_LMMI
N1W1:JCIBMUXOUTA2→ W1:JGRAYTEST4_PLL_CORE_I_PLL_LMMI
W1:JINTLOCK_PLL_CORE_I_PLL_LMMI→ W1:JINTLOCK_FBMUX_CORE_I_FBKMUX
N1W1:JCIBMUXOUTD0→ W1:JLEGACY_PLL_CORE_I_PLL_LMMI
W1:JLEGRDYN_PLL_CORE_I_PLL_LMMI→ W1:JLGYRDYN_FBMUX_CORE_I_FBKMUX
N1W1:JCLK1→ W1:JLMMICLK_PLL_CORE_I_PLL_LMMI
W1:JCIBMUXOUTB4→ W1:JLMMIOFFSET0_PLL_CORE_I_PLL_LMMI
W1:JCIBMUXOUTB5→ W1:JLMMIOFFSET1_PLL_CORE_I_PLL_LMMI
W1:JCIBMUXOUTB6→ W1:JLMMIOFFSET2_PLL_CORE_I_PLL_LMMI
W1:JCIBMUXOUTB7→ W1:JLMMIOFFSET3_PLL_CORE_I_PLL_LMMI
N1W1:JCIBMUXOUTC4→ W1:JLMMIOFFSET4_PLL_CORE_I_PLL_LMMI
N1W1:JCIBMUXOUTC5→ W1:JLMMIOFFSET5_PLL_CORE_I_PLL_LMMI
N1W1:JCIBMUXOUTC6→ W1:JLMMIOFFSET6_PLL_CORE_I_PLL_LMMI
W1:JCIBMUXOUTA6→ W1:JLMMIREQUEST_PLL_CORE_I_PLL_LMMI
W1:JLSR0→ W1:JLMMIRESETN_PLL_CORE_I_PLL_LMMI
W1:JCIBMUXOUTD2→ W1:JLMMIWDATA0_PLL_CORE_I_PLL_LMMI
W1:JCIBMUXOUTD3→ W1:JLMMIWDATA1_PLL_CORE_I_PLL_LMMI
W1:JCIBMUXOUTD4→ W1:JLMMIWDATA2_PLL_CORE_I_PLL_LMMI
W1:JCIBMUXOUTD5→ W1:JLMMIWDATA3_PLL_CORE_I_PLL_LMMI
N1W1:JCIBMUXOUTA4→ W1:JLMMIWDATA4_PLL_CORE_I_PLL_LMMI
N1W1:JCIBMUXOUTA5→ W1:JLMMIWDATA5_PLL_CORE_I_PLL_LMMI
N1W1:JCIBMUXOUTA6→ W1:JLMMIWDATA6_PLL_CORE_I_PLL_LMMI
N1W1:JCIBMUXOUTA7→ W1:JLMMIWDATA7_PLL_CORE_I_PLL_LMMI
W1:JCIBMUXOUTA7→ W1:JLMMIWRRDN_PLL_CORE_I_PLL_LMMI
S1W1:JCLK0→ W1:JOPCGLDCK_PLL_CORE_I_PLL_LMMI
N1W1:JCIBMUXOUTD2→ W1:JPLLPDN_PLL_CORE_I_PLL_LMMI
N1W1:JLSR0→ W1:JPLLRESET_PLL_CORE_I_PLL_LMMI
W1:JCLKOP_PLL_CORE_I_PLL_LMMI→ W1:JQ0
W1:JCLKOS_PLL_CORE_I_PLL_LMMI→ W1:JQ1
W1:JCLKOS2_PLL_CORE_I_PLL_LMMI→ W1:JQ2
W1:JCLKOS3_PLL_CORE_I_PLL_LMMI→ W1:JQ3
W1:JCLKOS4_PLL_CORE_I_PLL_LMMI→ W1:JQ4
W1:JCLKOS5_PLL_CORE_I_PLL_LMMI→ W1:JQ5
W1:JLMMIRDATA3_PLL_CORE_I_PLL_LMMI→ W1:JQ6
W1:JLMMIREADY_PLL_CORE_I_PLL_LMMI→ W1:JQ7
W1:JREFCK_REFMUX_CORE_I_REFMUX→ W1:JREFCK_PLL_CORE_I_PLL_LMMI
W1:JCLK0→ W1:JREFCLK11_REFMUX_CORE_I_REFMUX
S3W33:JINCK_IOLOGIC_CORE_I_GEARING_PIC_TOP_A→ W1:JREFCLK13_REFMUX_CORE_I_REFMUX
S3W33:JPADDI_DIFFIO18_CORE_IOA→ W1:JREFCLK13_REFMUX_CORE_I_REFMUX
S3W3:JINCK_IOLOGIC_CORE_I_GEARING_PIC_TOP_A→ W1:JREFCLK14_REFMUX_CORE_I_REFMUX
S3W3:JPADDI_DIFFIO18_CORE_IOA→ W1:JREFCLK14_REFMUX_CORE_I_REFMUX
S3W43:JINCK_IOLOGIC_CORE_I_GEARING_PIC_TOP_A→ W1:JREFCLK15_REFMUX_CORE_I_REFMUX
S3W43:JPADDI_DIFFIO18_CORE_IOA→ W1:JREFCLK15_REFMUX_CORE_I_REFMUX
N23:JINCK_SIOLOGIC_CORE_IBASE_PIC_A→ W1:JREFCLK16_REFMUX_CORE_I_REFMUX
N23:JPADDI_SEIO33_CORE_IOA→ W1:JREFCLK16_REFMUX_CORE_I_REFMUX
N1W1:JCLK0→ W1:JREFCLK21_REFMUX_CORE_I_REFMUX
S3W29:JINCK_IOLOGIC_CORE_I_GEARING_PIC_TOP_A→ W1:JREFCLK23_REFMUX_CORE_I_REFMUX
S3W29:JPADDI_DIFFIO18_CORE_IOA→ W1:JREFCLK23_REFMUX_CORE_I_REFMUX
S3W47:JINCK_IOLOGIC_CORE_I_GEARING_PIC_TOP_A→ W1:JREFCLK25_REFMUX_CORE_I_REFMUX
S3W47:JPADDI_DIFFIO18_CORE_IOA→ W1:JREFCLK25_REFMUX_CORE_I_REFMUX
N21:JINCK_SIOLOGIC_CORE_IBASE_PIC_A→ W1:JREFCLK26_REFMUX_CORE_I_REFMUX
N21:JPADDI_SEIO33_CORE_IOA→ W1:JREFCLK26_REFMUX_CORE_I_REFMUX
W1:JCIBMUXOUTB0→ W1:JREFSEL_REFMUX_CORE_I_REFMUX
N1W1:JCIBMUXOUTB7→ W1:JROTDELP1_PLL_CORE_I_PLL_LMMI
N1W1:JCIBMUXOUTB6→ W1:JROTDEL_PLL_CORE_I_PLL_LMMI
W1:JCIBMUXOUTD7→ W1:JSCANCLK_PLL_CORE_I_PLL_LMMI
N1W1:JLSR1→ W1:JSCANRST_PLL_CORE_I_PLL_LMMI
N1W1:JCIBMUXOUTD1→ W1:JSTDBY_PLL_CORE_I_PLL_LMMI
W1:JCIBMUXOUTB2→ W1:JWKUPSYNC_FBMUX_CORE_I_FBKMUX
W1:JZRSEL3_REFMUX_CORE_I_REFMUX→ W1:JZRSEL3_PLL_CORE_I_PLL_LMMI