GPLL_LLC_15K Tile Documentation

Tile Bels

NameType
PLL_LLC PLL_CORE

Config Bitmap

 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
F
F
F
 
 
R
R
R
 
 
R
R
R
 
 
F
F
F
F
 
M
 
R
 
L
 
 
 
 
 
 
 
 
 
 
 
L
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

Routing Muxes

Mux driving N1:JFBKCK_FBMUX_CORE_FBKMUX

Source F35B0 F36B0 F37B0 F38B0
N1:JFBKCLK0_FBMUX_CORE_FBKMUX - - - -
N1:JFBKCLK8_FBMUX_CORE_FBKMUX - - - 1
N1:JFBKCLK4_FBMUX_CORE_FBKMUX - - 1 -
N1:JFBKCLK12_FBMUX_CORE_FBKMUX - - 1 1
N1:JFBKCLK2_FBMUX_CORE_FBKMUX - 1 - -
N1:JFBKCLK10_FBMUX_CORE_FBKMUX - 1 - 1
N1:JFBKCLK6_FBMUX_CORE_FBKMUX - 1 1 -
N1:JFBKCLK14_FBMUX_CORE_FBKMUX - 1 1 1
N1:JFBKCLK1_FBMUX_CORE_FBKMUX 1 - - -
N1:JFBKCLK9_FBMUX_CORE_FBKMUX 1 - - 1
N1:JFBKCLK5_FBMUX_CORE_FBKMUX 1 - 1 -
N1:JFBKCLK13_FBMUX_CORE_FBKMUX 1 - 1 1
N1:JFBKCLK3_FBMUX_CORE_FBKMUX 1 1 - -
N1:JFBKCLK11_FBMUX_CORE_FBKMUX 1 1 - 1
N1:JFBKCLK7_FBMUX_CORE_FBKMUX 1 1 1 -
N1:JFBKCLK15_FBMUX_CORE_FBKMUX 1 1 1 1

Mux driving N1:JREFCK_REFMUX_CORE_REFMUX

Source F25B0 F26B0 F27B0 F30B0 F31B0 F32B0 F42B0
N1:JREFCLK10_REFMUX_CORE_REFMUX - - - - - - -
N1:JREFCLK20_REFMUX_CORE_REFMUX - - - - - - 1
N1:JREFCLK24_REFMUX_CORE_REFMUX - - - - - 1 1
N1:JREFCLK22_REFMUX_CORE_REFMUX - - - - 1 - 1
N1:JREFCLK26_REFMUX_CORE_REFMUX - - - - 1 1 1
N1:JREFCLK21_REFMUX_CORE_REFMUX - - - 1 - - 1
N1:JREFCLK25_REFMUX_CORE_REFMUX - - - 1 - 1 1
N1:JREFCLK23_REFMUX_CORE_REFMUX - - - 1 1 - 1
N1:JREFCLK27_REFMUX_CORE_REFMUX - - - 1 1 1 1
N1:JREFCLK14_REFMUX_CORE_REFMUX - - 1 - - - -
N1:JREFCLK12_REFMUX_CORE_REFMUX - 1 - - - - -
N1:JREFCLK16_REFMUX_CORE_REFMUX - 1 1 - - - -
N1:JREFCLK11_REFMUX_CORE_REFMUX 1 - - - - - -
N1:JREFCLK15_REFMUX_CORE_REFMUX 1 - 1 - - - -
N1:JREFCLK13_REFMUX_CORE_REFMUX 1 1 - - - - -
N1:JREFCLK17_REFMUX_CORE_REFMUX 1 1 1 - - - -

Configuration Enums

Configuration enum PLL_LLC.CLKMUX_FB

internal feedback selection

Value F20B0 F21B0 F22B0
CMUX_CLKOP - - -
CMUX_CLKOS 1 - -
CMUX_CLKOS2 - 1 -
CMUX_CLKOS3 1 1 -
CMUX_CLKOS4 - - 1
CMUX_CLKOS5 1 - 1

Configuration enum PLL_LLC.LMMICLKMUX

Value F44B0
INV 1
LMMICLK -

Configuration enum PLL_LLC.LMMIRESETNMUX

Value F56B0
INV 1
LMMIRESETN -

Configuration enum PLL_LLC.MODE

PLL_CORE primitive mode

Value F40B0
NONE -
PLL_CORE 1

Fixed Connections

SourceSink
N1:JCLKOP_PLL_CORE_PLL_LMMI G:JLLCLKOP_BMID_CORE_BMIDMUX
N1:JCLKOP_PLL_CORE_PLL_LMMI G:JLLCLKOP_ECLKBANK_CORE_ECLKBANK3
N1:JCLKOP_PLL_CORE_PLL_LMMI G:JLLCLKOP_ECLKBANK_CORE_ECLKBANK4
N1:JCLKOP_PLL_CORE_PLL_LMMI G:JLLCLKOP_ECLKBANK_CORE_ECLKBANK5
N1:JCLKOP_PLL_CORE_PLL_LMMI G:JLLCLKOP_ECLKLOGICMUXPLLFB_CORE_ECLKPLLFBR
N1:JCLKOP_PLL_CORE_PLL_LMMI G:JLLCLKOP_LMID_CORE_LMIDMUX
N1:JCLKOS2_PLL_CORE_PLL_LMMI G:JLLCLKOS2_BMID_CORE_BMIDMUX
N1:JCLKOS2_PLL_CORE_PLL_LMMI G:JLLCLKOS2_ECLKBANK_CORE_ECLKBANK3
N1:JCLKOS2_PLL_CORE_PLL_LMMI G:JLLCLKOS2_ECLKBANK_CORE_ECLKBANK4
N1:JCLKOS2_PLL_CORE_PLL_LMMI G:JLLCLKOS2_ECLKBANK_CORE_ECLKBANK5
N1:JCLKOS2_PLL_CORE_PLL_LMMI G:JLLCLKOS2_ECLKLOGICMUXPLLFB_CORE_ECLKPLLFBR
N1:JCLKOS2_PLL_CORE_PLL_LMMI G:JLLCLKOS2_LMID_CORE_LMIDMUX
N1:JCLKOS3_PLL_CORE_PLL_LMMI G:JLLCLKOS3_BMID_CORE_BMIDMUX
N1:JCLKOS3_PLL_CORE_PLL_LMMI G:JLLCLKOS3_ECLKBANK_CORE_ECLKBANK3
N1:JCLKOS3_PLL_CORE_PLL_LMMI G:JLLCLKOS3_ECLKBANK_CORE_ECLKBANK4
N1:JCLKOS3_PLL_CORE_PLL_LMMI G:JLLCLKOS3_ECLKBANK_CORE_ECLKBANK5
N1:JCLKOS3_PLL_CORE_PLL_LMMI G:JLLCLKOS3_ECLKLOGICMUXPLLFB_CORE_ECLKPLLFBR
N1:JCLKOS3_PLL_CORE_PLL_LMMI G:JLLCLKOS3_LMID_CORE_LMIDMUX
N1:JCLKOS4_PLL_CORE_PLL_LMMI G:JLLCLKOS4_BMID_CORE_BMIDMUX
N1:JCLKOS4_PLL_CORE_PLL_LMMI G:JLLCLKOS4_ECLKBANK_CORE_ECLKBANK3
N1:JCLKOS4_PLL_CORE_PLL_LMMI G:JLLCLKOS4_ECLKBANK_CORE_ECLKBANK4
N1:JCLKOS4_PLL_CORE_PLL_LMMI G:JLLCLKOS4_ECLKBANK_CORE_ECLKBANK5
N1:JCLKOS4_PLL_CORE_PLL_LMMI G:JLLCLKOS4_ECLKLOGICMUXPLLFB_CORE_ECLKPLLFBR
N1:JCLKOS4_PLL_CORE_PLL_LMMI G:JLLCLKOS4_LMID_CORE_LMIDMUX
N1:JCLKOS5_PLL_CORE_PLL_LMMI G:JLLCLKOS5_BMID_CORE_BMIDMUX
N1:JCLKOS5_PLL_CORE_PLL_LMMI G:JLLCLKOS5_ECLKBANK_CORE_ECLKBANK3
N1:JCLKOS5_PLL_CORE_PLL_LMMI G:JLLCLKOS5_ECLKBANK_CORE_ECLKBANK4
N1:JCLKOS5_PLL_CORE_PLL_LMMI G:JLLCLKOS5_ECLKBANK_CORE_ECLKBANK5
N1:JCLKOS5_PLL_CORE_PLL_LMMI G:JLLCLKOS5_ECLKLOGICMUXPLLFB_CORE_ECLKPLLFBR
N1:JCLKOS5_PLL_CORE_PLL_LMMI G:JLLCLKOS5_LMID_CORE_LMIDMUX
N1:JCLKOS_PLL_CORE_PLL_LMMI G:JLLCLKOS_BMID_CORE_BMIDMUX
N1:JCLKOS_PLL_CORE_PLL_LMMI G:JLLCLKOS_ECLKBANK_CORE_ECLKBANK3
N1:JCLKOS_PLL_CORE_PLL_LMMI G:JLLCLKOS_ECLKBANK_CORE_ECLKBANK4
N1:JCLKOS_PLL_CORE_PLL_LMMI G:JLLCLKOS_ECLKBANK_CORE_ECLKBANK5
N1:JCLKOS_PLL_CORE_PLL_LMMI G:JLLCLKOS_ECLKLOGICMUXPLLFB_CORE_ECLKPLLFBR
N1:JCLKOS_PLL_CORE_PLL_LMMI G:JLLCLKOS_LMID_CORE_LMIDMUX
N1:JCIBMUXOUTB0 N1:JBINACT0_PLL_CORE_PLL_LMMI
N1:JCIBMUXOUTB1 N1:JBINACT1_PLL_CORE_PLL_LMMI
N1:JCIBMUXOUTB2 N1:JBINTEST0_PLL_CORE_PLL_LMMI
N1:JCIBMUXOUTB3 N1:JBINTEST1_PLL_CORE_PLL_LMMI
N1E1:JCIBMUXOUTC4 N1:JCIBDIR_PLL_CORE_PLL_LMMI
N1E1:JCIBMUXOUTC2 N1:JCIBDSEL0_PLL_CORE_PLL_LMMI
N1E1:JCIBMUXOUTC1 N1:JCIBDSEL1_PLL_CORE_PLL_LMMI
N1E1:JCIBMUXOUTC0 N1:JCIBDSEL2_PLL_CORE_PLL_LMMI
N1E1:JCIBMUXOUTB3 N1:JCIBLDREG_PLL_CORE_PLL_LMMI
N1E1:JCIBMUXOUTC3 N1:JCIBROT_PLL_CORE_PLL_LMMI
N1:JCIBMUXOUTB5 N1:JDIRDELP1_PLL_CORE_PLL_LMMI
N1:JCIBMUXOUTB4 N1:JDIRDEL_PLL_CORE_PLL_LMMI
N1E1:JCIBMUXOUTA0 N1:JENCLKOP_PLL_CORE_PLL_LMMI
N1E1:JCIBMUXOUTA2 N1:JENCLKOS2_PLL_CORE_PLL_LMMI
N1E1:JCIBMUXOUTA3 N1:JENCLKOS3_PLL_CORE_PLL_LMMI
N1E1:JCIBMUXOUTA4 N1:JENCLKOS4_PLL_CORE_PLL_LMMI
N1E1:JCIBMUXOUTA5 N1:JENCLKOS5_PLL_CORE_PLL_LMMI
N1E1:JCIBMUXOUTA1 N1:JENCLKOS_PLL_CORE_PLL_LMMI
N1:JENEXT_FBMUX_CORE_FBKMUX N1:JENEXT_PLL_CORE_PLL_LMMI
N1:JLMMIRDATAVALID_PLL_CORE_PLL_LMMI N1:JF3
N1:JLMMIRDATA4_PLL_CORE_PLL_LMMI N1:JF4
N1:JLMMIRDATA5_PLL_CORE_PLL_LMMI N1:JF5
N1:JLMMIRDATA6_PLL_CORE_PLL_LMMI N1:JF6
N1:JLMMIRDATA7_PLL_CORE_PLL_LMMI N1:JF7
N1:JFBKCK_FBMUX_CORE_FBKMUX N1:JFBKCK_PLL_CORE_PLL_LMMI
N1:JINTFBK0_PLL_CORE_PLL_LMMI N1:JFBKCLK0_FBMUX_CORE_FBKMUX
N1E34:JECLKOUT_ECLKLOGICMUXPLLFB_CORE_ECLKPLLFBL N1:JFBKCLK10_FBMUX_CORE_FBKMUX
N1E1:JCLK1 N1:JFBKCLK11_FBMUX_CORE_FBKMUX
N1:JINTFBK1_PLL_CORE_PLL_LMMI N1:JFBKCLK1_FBMUX_CORE_FBKMUX
N1:JINTFBK2_PLL_CORE_PLL_LMMI N1:JFBKCLK2_FBMUX_CORE_FBKMUX
N1:JINTFBK3_PLL_CORE_PLL_LMMI N1:JFBKCLK3_FBMUX_CORE_FBKMUX
N1:JINTFBK4_PLL_CORE_PLL_LMMI N1:JFBKCLK4_FBMUX_CORE_FBKMUX
N1:JINTFBK5_PLL_CORE_PLL_LMMI N1:JFBKCLK5_FBMUX_CORE_FBKMUX
N1:JCLKOUTDL_PLL_CORE_PLL_LMMI N1:JFBKCLK6_FBMUX_CORE_FBKMUX
N1:JCIBMUXOUTC0 N1:JGRAYACT0_PLL_CORE_PLL_LMMI
N1:JCIBMUXOUTC1 N1:JGRAYACT1_PLL_CORE_PLL_LMMI
N1:JCIBMUXOUTC2 N1:JGRAYACT2_PLL_CORE_PLL_LMMI
N1:JCIBMUXOUTC3 N1:JGRAYACT3_PLL_CORE_PLL_LMMI
N1:JCIBMUXOUTA0 N1:JGRAYACT4_PLL_CORE_PLL_LMMI
N1:JCIBMUXOUTD3 N1:JGRAYTEST0_PLL_CORE_PLL_LMMI
N1:JCIBMUXOUTD4 N1:JGRAYTEST1_PLL_CORE_PLL_LMMI
N1:JCIBMUXOUTD5 N1:JGRAYTEST2_PLL_CORE_PLL_LMMI
N1:JCIBMUXOUTD6 N1:JGRAYTEST3_PLL_CORE_PLL_LMMI
N1:JCIBMUXOUTA2 N1:JGRAYTEST4_PLL_CORE_PLL_LMMI
N1:JINTLOCK_PLL_CORE_PLL_LMMI N1:JINTLOCK_FBMUX_CORE_FBKMUX
N1:JCIBMUXOUTD0 N1:JLEGACY_PLL_CORE_PLL_LMMI
N1:JLEGRDYN_PLL_CORE_PLL_LMMI N1:JLGYRDYN_FBMUX_CORE_FBKMUX
N1:JCLK1 N1:JLMMICLK_PLL_CORE_PLL_LMMI
N1E1:JCIBMUXOUTB4 N1:JLMMIOFFSET0_PLL_CORE_PLL_LMMI
N1E1:JCIBMUXOUTB5 N1:JLMMIOFFSET1_PLL_CORE_PLL_LMMI
N1E1:JCIBMUXOUTB6 N1:JLMMIOFFSET2_PLL_CORE_PLL_LMMI
N1E1:JCIBMUXOUTB7 N1:JLMMIOFFSET3_PLL_CORE_PLL_LMMI
N1:JCIBMUXOUTC4 N1:JLMMIOFFSET4_PLL_CORE_PLL_LMMI
N1:JCIBMUXOUTC5 N1:JLMMIOFFSET5_PLL_CORE_PLL_LMMI
N1:JCIBMUXOUTC6 N1:JLMMIOFFSET6_PLL_CORE_PLL_LMMI
N1E1:JCIBMUXOUTA6 N1:JLMMIREQUEST_PLL_CORE_PLL_LMMI
N1E1:JLSR0 N1:JLMMIRESETN_PLL_CORE_PLL_LMMI
N1E1:JCIBMUXOUTD2 N1:JLMMIWDATA0_PLL_CORE_PLL_LMMI
N1E1:JCIBMUXOUTD3 N1:JLMMIWDATA1_PLL_CORE_PLL_LMMI
N1E1:JCIBMUXOUTD4 N1:JLMMIWDATA2_PLL_CORE_PLL_LMMI
N1E1:JCIBMUXOUTD5 N1:JLMMIWDATA3_PLL_CORE_PLL_LMMI
N1:JCIBMUXOUTA4 N1:JLMMIWDATA4_PLL_CORE_PLL_LMMI
N1:JCIBMUXOUTA5 N1:JLMMIWDATA5_PLL_CORE_PLL_LMMI
N1:JCIBMUXOUTA6 N1:JLMMIWDATA6_PLL_CORE_PLL_LMMI
N1:JCIBMUXOUTA7 N1:JLMMIWDATA7_PLL_CORE_PLL_LMMI
N1E1:JCIBMUXOUTA7 N1:JLMMIWRRDN_PLL_CORE_PLL_LMMI
N1E2:JCLK0 N1:JOPCGLDCK_PLL_CORE_PLL_LMMI
N1:JCIBMUXOUTD2 N1:JPLLPDN_PLL_CORE_PLL_LMMI
N1:JLSR1 N1:JPLLRESET_PLL_CORE_PLL_LMMI
N1:JREGQA_PLL_CORE_PLL_LMMI N1:JQ0
N1:JREGQB_PLL_CORE_PLL_LMMI N1:JQ1
N1:JREGQB1_PLL_CORE_PLL_LMMI N1:JQ2
N1:JREFDETLOS_PLL_CORE_PLL_LMMI N1:JQ4
N1:JREFCK_REFMUX_CORE_REFMUX N1:JREFCK_PLL_CORE_PLL_LMMI
N1E1:JCLK0 N1:JREFCLK11_REFMUX_CORE_REFMUX
E19:JINCK_IOLOGIC_CORE_I_GEARING_PIC_TOP_A N1:JREFCLK14_REFMUX_CORE_REFMUX
E19:JPADDI_DIFFIO18_CORE_IOA N1:JREFCLK14_REFMUX_CORE_REFMUX
E53:JINCK_IOLOGIC_CORE_I_GEARING_PIC_TOP_A N1:JREFCLK15_REFMUX_CORE_REFMUX
E53:JPADDI_DIFFIO18_CORE_IOA N1:JREFCLK15_REFMUX_CORE_REFMUX
E17:JINCK_IOLOGIC_CORE_I_GEARING_PIC_TOP_A N1:JREFCLK16_REFMUX_CORE_REFMUX
E17:JPADDI_DIFFIO18_CORE_IOA N1:JREFCLK16_REFMUX_CORE_REFMUX
N1:JCLK0 N1:JREFCLK21_REFMUX_CORE_REFMUX
E51:JINCK_IOLOGIC_CORE_I_GEARING_PIC_TOP_A N1:JREFCLK25_REFMUX_CORE_REFMUX
E51:JPADDI_DIFFIO18_CORE_IOA N1:JREFCLK25_REFMUX_CORE_REFMUX
E19:JINCK_IOLOGIC_CORE_I_GEARING_PIC_TOP_A N1:JREFCLK26_REFMUX_CORE_REFMUX
E19:JPADDI_DIFFIO18_CORE_IOA N1:JREFCLK26_REFMUX_CORE_REFMUX
N1:JCIBMUXOUTA1 N1:JREFDETRESET_PLL_CORE_PLL_LMMI
N1E1:JCIBMUXOUTB0 N1:JREFSEL_REFMUX_CORE_REFMUX
N1:JCIBMUXOUTB7 N1:JROTDELP1_PLL_CORE_PLL_LMMI
N1:JCIBMUXOUTB6 N1:JROTDEL_PLL_CORE_PLL_LMMI
N1E1:JCIBMUXOUTD7 N1:JSCANCLK_PLL_CORE_PLL_LMMI
N1:JLSR0 N1:JSCANRST_PLL_CORE_PLL_LMMI
N1:JCIBMUXOUTD1 N1:JSTDBY_PLL_CORE_PLL_LMMI
N1E1:JCIBMUXOUTB2 N1:JWKUPSYNC_FBMUX_CORE_FBKMUX
N1:JZRSEL3_REFMUX_CORE_REFMUX N1:JZRSEL3_PLL_CORE_PLL_LMMI
N1:JREFMUXCK_PLL_CORE_PLL_LMMI N1E1:JF0
N1:JLOCK_PLL_CORE_PLL_LMMI N1E1:JF1
N1:JINTLOCK_PLL_CORE_PLL_LMMI N1E1:JF2
N1:JPFDUP_PLL_CORE_PLL_LMMI N1E1:JF3
N1:JPFDDN_PLL_CORE_PLL_LMMI N1E1:JF4
N1:JLMMIRDATA0_PLL_CORE_PLL_LMMI N1E1:JF5
N1:JLMMIRDATA1_PLL_CORE_PLL_LMMI N1E1:JF6
N1:JLMMIRDATA2_PLL_CORE_PLL_LMMI N1E1:JF7
N1:JCLKOP_PLL_CORE_PLL_LMMI N1E1:JQ0
N1:JCLKOS_PLL_CORE_PLL_LMMI N1E1:JQ1
N1:JCLKOS2_PLL_CORE_PLL_LMMI N1E1:JQ2
N1:JCLKOS3_PLL_CORE_PLL_LMMI N1E1:JQ3
N1:JCLKOS4_PLL_CORE_PLL_LMMI N1E1:JQ4
N1:JCLKOS5_PLL_CORE_PLL_LMMI N1E1:JQ5
N1:JLMMIRDATA3_PLL_CORE_PLL_LMMI N1E1:JQ6
N1:JLMMIREADY_PLL_CORE_PLL_LMMI N1E1:JQ7
N1:JCLKOP_PLL_CORE_PLL_LMMI N1E34:JLLCLKOP_ECLKLOGICMUXPLLFB_CORE_ECLKPLLFBL
N1:JCLKOS2_PLL_CORE_PLL_LMMI N1E34:JLLCLKOS2_ECLKLOGICMUXPLLFB_CORE_ECLKPLLFBL
N1:JCLKOS3_PLL_CORE_PLL_LMMI N1E34:JLLCLKOS3_ECLKLOGICMUXPLLFB_CORE_ECLKPLLFBL
N1:JCLKOS4_PLL_CORE_PLL_LMMI N1E34:JLLCLKOS4_ECLKLOGICMUXPLLFB_CORE_ECLKPLLFBL
N1:JCLKOS5_PLL_CORE_PLL_LMMI N1E34:JLLCLKOS5_ECLKLOGICMUXPLLFB_CORE_ECLKPLLFBL
N1:JCLKOS_PLL_CORE_PLL_LMMI N1E34:JLLCLKOS_ECLKLOGICMUXPLLFB_CORE_ECLKPLLFBL
N1:JCLKOP_PLL_CORE_PLL_LMMI N1E3:JSREFCLK_SGMIICDR_CORE
N1:JCLKOP_PLL_CORE_PLL_LMMI N1E4:JSREFCLK_SGMIICDR_CORE