EFB_15K Tile Documentation

Config Bitmap

 
 
 
 
 
E
 
 
1
D
E
 
M
 
M
 
M
 
M
M
M
M
M
M
M
M
M
M
M
M
 
 
M
M
 
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
S
 
T
 
M
 
M
M
M
 
 
 
 
1
 
 
 
T
 
T
S
 
 
 
P
 
P
P
P
P
P
M
 
W
 
 
S
 
S
S
M
 
M
M
W
 
 
W
W
 
D
D
 
 
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
 
P
P
M
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

Configuration Words

Configuration word CONFIG_IP_CORE.DSRFCTRL

CONFIG_IP_CORE.DSRFCTRL[0]F101B0
CONFIG_IP_CORE.DSRFCTRL[1]F102B0

Configuration word CONFIG_MULTIBOOT_CORE.MSPIADDR

SPI flash fixed next address

CONFIG_MULTIBOOT_CORE.MSPIADDR[0]F24B0
CONFIG_MULTIBOOT_CORE.MSPIADDR[1]F25B0
CONFIG_MULTIBOOT_CORE.MSPIADDR[2]F26B0
CONFIG_MULTIBOOT_CORE.MSPIADDR[3]F27B0
CONFIG_MULTIBOOT_CORE.MSPIADDR[4]F28B0
CONFIG_MULTIBOOT_CORE.MSPIADDR[5]F29B0
CONFIG_MULTIBOOT_CORE.MSPIADDR[6]F32B0
CONFIG_MULTIBOOT_CORE.MSPIADDR[7]F33B0
CONFIG_MULTIBOOT_CORE.MSPIADDR[8]F35B0
CONFIG_MULTIBOOT_CORE.MSPIADDR[9]F36B0
CONFIG_MULTIBOOT_CORE.MSPIADDR[10]F37B0
CONFIG_MULTIBOOT_CORE.MSPIADDR[11]F38B0
CONFIG_MULTIBOOT_CORE.MSPIADDR[12]F39B0
CONFIG_MULTIBOOT_CORE.MSPIADDR[13]F40B0
CONFIG_MULTIBOOT_CORE.MSPIADDR[14]F41B0
CONFIG_MULTIBOOT_CORE.MSPIADDR[15]F42B0
CONFIG_MULTIBOOT_CORE.MSPIADDR[16]F43B0
CONFIG_MULTIBOOT_CORE.MSPIADDR[17]F44B0
CONFIG_MULTIBOOT_CORE.MSPIADDR[18]F45B0
CONFIG_MULTIBOOT_CORE.MSPIADDR[19]F46B0
CONFIG_MULTIBOOT_CORE.MSPIADDR[20]F47B0
CONFIG_MULTIBOOT_CORE.MSPIADDR[21]F48B0
CONFIG_MULTIBOOT_CORE.MSPIADDR[22]F49B0
CONFIG_MULTIBOOT_CORE.MSPIADDR[23]F50B0
CONFIG_MULTIBOOT_CORE.MSPIADDR[24]F14B0
CONFIG_MULTIBOOT_CORE.MSPIADDR[25]F16B0
CONFIG_MULTIBOOT_CORE.MSPIADDR[26]F18B0
CONFIG_MULTIBOOT_CORE.MSPIADDR[27]F19B0
CONFIG_MULTIBOOT_CORE.MSPIADDR[28]F20B0
CONFIG_MULTIBOOT_CORE.MSPIADDR[29]F21B0
CONFIG_MULTIBOOT_CORE.MSPIADDR[30]F22B0
CONFIG_MULTIBOOT_CORE.MSPIADDR[31]F23B0

Configuration word CONFIG_WDT_CORE.WDTVALUE

watchdog timer timeout count

CONFIG_WDT_CORE.WDTVALUE[0]F99B0
CONFIG_WDT_CORE.WDTVALUE[1]F105B0
CONFIG_WDT_CORE.WDTVALUE[2]F0B1
CONFIG_WDT_CORE.WDTVALUE[3]F1B1
CONFIG_WDT_CORE.WDTVALUE[4]F2B1
CONFIG_WDT_CORE.WDTVALUE[5]F3B1
CONFIG_WDT_CORE.WDTVALUE[6]F4B1
CONFIG_WDT_CORE.WDTVALUE[7]F5B1
CONFIG_WDT_CORE.WDTVALUE[8]F6B1
CONFIG_WDT_CORE.WDTVALUE[9]F7B1
CONFIG_WDT_CORE.WDTVALUE[10]F8B1
CONFIG_WDT_CORE.WDTVALUE[11]F9B1
CONFIG_WDT_CORE.WDTVALUE[12]F10B1
CONFIG_WDT_CORE.WDTVALUE[13]F11B1
CONFIG_WDT_CORE.WDTVALUE[14]F12B1
CONFIG_WDT_CORE.WDTVALUE[15]F13B1
CONFIG_WDT_CORE.WDTVALUE[16]F14B1
CONFIG_WDT_CORE.WDTVALUE[17]F15B1

Configuration Enums

Configuration enum CONFIG_CLKRST_CORE.MCJTAGGSRNDIS

Value F59B0
DIS 1
EN -

Configuration enum CONFIG_CLKRST_CORE.MCLMMIGSRNDIS

Value F55B0
DIS 1
EN -

Configuration enum CONFIG_CLKRST_CORE.MCSEDCGSRNDIS

Value F57B0
DIS 1
EN -

Configuration enum CONFIG_CLKRST_CORE.MCWDTGSRNDIS

Value F58B0
DIS 1
EN -

Configuration enum CONFIG_CRE_CORE.MODE

CONFIG_CRE_CORE primitive mode

Value F12B0
CONFIG_CRE_CORE 1
NONE -

Configuration enum CONFIG_IP_CORE.DONEPHASE

changes point at which DONE is asserted during startup

Value F9B0
DIS -
EN 1

Configuration enum CONFIG_IP_CORE.ENTSALL

Value F10B0
DIS -
EN 1

Configuration enum CONFIG_IP_CORE.MCCIBINT

Value F93B0
DIS 1
EN -

Configuration enum CONFIG_IP_CORE.MCJTAGDISABLE

Value F19B1
DIS 1
EN -

Configuration enum CONFIG_IP_CORE.MCPERSISTUI2C

keep user I2C open after configuration

Value F82B0
DIS 1
EN -

Configuration enum CONFIG_IP_CORE.MCUCLKSEL

Value F91B0
DIS 1
EN -

Configuration enum CONFIG_IP_CORE.MCUI2CAFWKUP

Value F94B0
DIS 1
EN -

Configuration enum CONFIG_IP_CORE.PERSISTI2C

keep I2C open after configuration

Value F81B0
DIS -
EN 1

Configuration enum CONFIG_IP_CORE.PERSISTI3C

keep I3C open after configuration

Value F17B1
DIS -
EN 1

Configuration enum CONFIG_IP_CORE.PERSISTMQUAD

keep master QSPI open after configuration

Value F78B0
DIS -
EN 1

Configuration enum CONFIG_IP_CORE.PERSISTMSPI

keep master SPI open after configuration

Value F75B0
DIS -
EN 1

Configuration enum CONFIG_IP_CORE.PERSISTSHEXA

keep slave 16-bit 'SPI' open after configuration

Value F18B1
DIS -
EN 1

Configuration enum CONFIG_IP_CORE.PERSISTSOCTA

keep slave 8-bit 'SPI' open after configuration

Value F80B0
DIS -
EN 1

Configuration enum CONFIG_IP_CORE.PERSISTSQUAD

keep slave QSPI open after configuration

Value F79B0
DIS -
EN 1

Configuration enum CONFIG_IP_CORE.PERSISTSSPI

keep slave SPI open after configuration

Value F77B0
DIS -
EN 1

Configuration enum CONFIG_IP_CORE.SCANEN

Value F87B0 F89B0 F90B0
DIS - - -
EN 1 1 1

Configuration enum CONFIG_IP_CORE.SYNCEXTDONE

Value F51B0
DIS -
EN 1

Configuration enum CONFIG_IP_CORE.TRANECI

Value F68B0
DIS -
EN 1

Configuration enum CONFIG_IP_CORE.TRANHSE

Value F53B0
DIS -
EN 1

Configuration enum CONFIG_IP_CORE.TRANSBI

Value F70B0
DIS -
EN 1

Configuration enum CONFIG_IP_CORE.WLSLEW

Value F84B0
DIS -
EN 1

Configuration enum CONFIG_LMMI_CORE.LMMI_EN

enable LMMI access to configuration

Value F5B0
DIS -
EN 1

Configuration enum CONFIG_MULTIBOOT_CORE.SOURCESEL

selects next address from input pins or fixed parameter

Value F71B0
DIS -
EN 1

Configuration enum CONFIG_WDT_CORE.WDTEN

enable watchdog timer

Value F95B0
DIS -
EN 1

Configuration enum CONFIG_WDT_CORE.WDTMODE

watchdog timer mode

Value F98B0
CONTINUOUS 1
SINGLE -

Configuration enum SYSCONFIG.MASTER_SPI_PORT

status of master SPI port after configuration

Value F75B0 F78B0
DISABLE - -
DUAL 1 -
QUAD 1 1
SERIAL 1 -

Configuration enum SYSCONFIG.SLAVE_I2C_PORT

status of slave I2C port after configuration

Value F81B0
DISABLE -
ENABLE 1

Configuration enum SYSCONFIG.SLAVE_I3C_PORT

status of slave I3C port after configuration

Value F17B1
DISABLE -
ENABLE 1

Configuration enum SYSCONFIG.SLAVE_SPI_PORT

status of slave SPI port after configuration

Value F77B0 F79B0
DISABLE - -
DUAL 1 -
QUAD 1 1
SERIAL 1 -

Fixed Connections

SourceSink
W14:JFREEZEIOCIB_CONFIG_IP_CORE_CONFIG_IP→ S1E2:JQ5
W14:JCFG_CLK_CONFIG_CLKRST_CORE_CONFIG_CLKRST→ S1E3:JF5
W14:JASFFULLO_CONFIG_CRE_CORE_CONFIG_HSE→ S1E3:JF6
W14:JASFEMPTYO_CONFIG_CRE_CORE_CONFIG_HSE→ S1E3:JF7
W14:JLASTADDRCIB8_CONFIG_IP_CORE_CONFIG_IP→ S1E5:JF0
W14:JLASTADDRCIB9_CONFIG_IP_CORE_CONFIG_IP→ S1E5:JF1
W14:JLASTADDRCIB10_CONFIG_IP_CORE_CONFIG_IP→ S1E5:JF2
W14:JLASTADDRCIB11_CONFIG_IP_CORE_CONFIG_IP→ S1E5:JF3
W14:JLASTADDRCIB12_CONFIG_IP_CORE_CONFIG_IP→ S1E5:JF4
W14:JLASTADDRCIB13_CONFIG_IP_CORE_CONFIG_IP→ S1E5:JF5
W14:JLASTADDRCIB14_CONFIG_IP_CORE_CONFIG_IP→ S1E5:JF6
W14:JLASTADDRCIB15_CONFIG_IP_CORE_CONFIG_IP→ S1E5:JF7
W14:JLASTADDRCIB0_CONFIG_IP_CORE_CONFIG_IP→ S1E5:JQ0
W14:JLASTADDRCIB1_CONFIG_IP_CORE_CONFIG_IP→ S1E5:JQ1
W14:JLASTADDRCIB2_CONFIG_IP_CORE_CONFIG_IP→ S1E5:JQ2
W14:JLASTADDRCIB3_CONFIG_IP_CORE_CONFIG_IP→ S1E5:JQ3
W14:JLASTADDRCIB4_CONFIG_IP_CORE_CONFIG_IP→ S1E5:JQ4
W14:JLASTADDRCIB5_CONFIG_IP_CORE_CONFIG_IP→ S1E5:JQ5
W14:JLASTADDRCIB6_CONFIG_IP_CORE_CONFIG_IP→ S1E5:JQ6
W14:JLASTADDRCIB7_CONFIG_IP_CORE_CONFIG_IP→ S1E5:JQ7
W14:JLMMIRDATA28_CONFIG_CRE_CORE_CONFIG_HSE→ S1W10:JF0
W14:JLMMIRDATA29_CONFIG_CRE_CORE_CONFIG_HSE→ S1W10:JF1
W14:JLMMIRDATA30_CONFIG_CRE_CORE_CONFIG_HSE→ S1W10:JF2
W14:JLMMIRDATA31_CONFIG_CRE_CORE_CONFIG_HSE→ S1W10:JF3
W14:JLMMIRDATA20_CONFIG_CRE_CORE_CONFIG_HSE→ S1W11:JF0
W14:JLMMIRDATA21_CONFIG_CRE_CORE_CONFIG_HSE→ S1W11:JF1
W14:JLMMIRDATA22_CONFIG_CRE_CORE_CONFIG_HSE→ S1W11:JF2
W14:JLMMIRDATA23_CONFIG_CRE_CORE_CONFIG_HSE→ S1W11:JF3
W14:JLMMIRDATA24_CONFIG_CRE_CORE_CONFIG_HSE→ S1W11:JF4
W14:JLMMIRDATA25_CONFIG_CRE_CORE_CONFIG_HSE→ S1W11:JF5
W14:JLMMIRDATA26_CONFIG_CRE_CORE_CONFIG_HSE→ S1W11:JF6
W14:JLMMIRDATA27_CONFIG_CRE_CORE_CONFIG_HSE→ S1W11:JF7
W14:JLMMIRDATAVALID_CONFIG_CRE_CORE_CONFIG_HSE→ S1W12:JF0
W14:JLMMIREADY_CONFIG_CRE_CORE_CONFIG_HSE→ S1W12:JF1
W14:JLMMIRDATA14_CONFIG_CRE_CORE_CONFIG_HSE→ S1W12:JF2
W14:JLMMIRDATA15_CONFIG_CRE_CORE_CONFIG_HSE→ S1W12:JF3
W14:JLMMIRDATA16_CONFIG_CRE_CORE_CONFIG_HSE→ S1W12:JF4
W14:JLMMIRDATA17_CONFIG_CRE_CORE_CONFIG_HSE→ S1W12:JF5
W14:JLMMIRDATA18_CONFIG_CRE_CORE_CONFIG_HSE→ S1W12:JF6
W14:JLMMIRDATA19_CONFIG_CRE_CORE_CONFIG_HSE→ S1W12:JF7
W14:JLMMIRDATA7_CONFIG_CRE_CORE_CONFIG_HSE→ S1W13:JF0
W14:JLMMIRDATA8_CONFIG_CRE_CORE_CONFIG_HSE→ S1W13:JF1
W14:JLMMIRDATA9_CONFIG_CRE_CORE_CONFIG_HSE→ S1W13:JF2
W14:JLMMIRDATA10_CONFIG_CRE_CORE_CONFIG_HSE→ S1W13:JF3
W14:JLMMIRDATA11_CONFIG_CRE_CORE_CONFIG_HSE→ S1W13:JF4
W14:JLMMIRDATA12_CONFIG_CRE_CORE_CONFIG_HSE→ S1W13:JF6
W14:JLMMIRDATA13_CONFIG_CRE_CORE_CONFIG_HSE→ S1W13:JF7
W14:JLMMIRDATA0_CONFIG_CRE_CORE_CONFIG_HSE→ S1W14:JF1
W14:JLMMIRDATA1_CONFIG_CRE_CORE_CONFIG_HSE→ S1W14:JF2
W14:JLMMIRDATA2_CONFIG_CRE_CORE_CONFIG_HSE→ S1W14:JF3
W14:JLMMIRDATA3_CONFIG_CRE_CORE_CONFIG_HSE→ S1W14:JF4
W14:JLMMIRDATA4_CONFIG_CRE_CORE_CONFIG_HSE→ S1W14:JF5
W14:JLMMIRDATA5_CONFIG_CRE_CORE_CONFIG_HSE→ S1W14:JF6
W14:JLMMIRDATA6_CONFIG_CRE_CORE_CONFIG_HSE→ S1W14:JF7
W14:JMBISTRRMATCH_CONFIG_IP_CORE_CONFIG_IP→ S1W2:JF0
W14:JCFGDONECIB_CONFIG_IP_CORE_CONFIG_IP→ S1W2:JF1
W14:JLMMIRDATA0_CONFIG_LMMI_CORE_LMMI_MODEL→ S1W4:JF0
W14:JLMMIRDATA1_CONFIG_LMMI_CORE_LMMI_MODEL→ S1W4:JF1
W14:JLMMIRDATA2_CONFIG_LMMI_CORE_LMMI_MODEL→ S1W4:JF2
W14:JLMMIRDATA3_CONFIG_LMMI_CORE_LMMI_MODEL→ S1W4:JF3
W14:JLMMIRDATA4_CONFIG_LMMI_CORE_LMMI_MODEL→ S1W4:JF4
W14:JLMMIRDATA5_CONFIG_LMMI_CORE_LMMI_MODEL→ S1W4:JF5
W14:JLMMIRDATA6_CONFIG_LMMI_CORE_LMMI_MODEL→ S1W4:JF6
W14:JLMMIRDATA7_CONFIG_LMMI_CORE_LMMI_MODEL→ S1W4:JF7
W14:JLMMIREADY_CONFIG_LMMI_CORE_LMMI_MODEL→ S1W4:JQ0
W14:JLMMIRDATAVALID_CONFIG_LMMI_CORE_LMMI_MODEL→ S1W4:JQ1
S1W2:JCLK0→ W14:JASFCLKI_CONFIG_CRE_CORE_CONFIG_HSE
S1:JCIBMUXOUTC1→ W14:JASFRDI_CONFIG_CRE_CORE_CONFIG_HSE
S1W2:JLSR0→ W14:JASFRESETI_CONFIG_CRE_CORE_CONFIG_HSE
S1:JCIBMUXOUTC0→ W14:JASFWRI_CONFIG_CRE_CORE_CONFIG_HSE
W14:JCFG_CLK_CONFIG_CLKRST_CORE_CONFIG_CLKRST→ W14:JCFG_CLK_CONFIG_CRE_CORE_CONFIG_HSE
S1W6:JCIBMUXOUTA0→ W14:JCIBAUTOREBOOT_CONFIG_MULTIBOOT_CORE_CONFIG_MULTIBOOT
S1W6:JCIBMUXOUTA1→ W14:JCIBMSPIMADDR0_CONFIG_MULTIBOOT_CORE_CONFIG_MULTIBOOT
S1W5:JCIBMUXOUTA6→ W14:JCIBMSPIMADDR10_CONFIG_MULTIBOOT_CORE_CONFIG_MULTIBOOT
S1W5:JCIBMUXOUTA7→ W14:JCIBMSPIMADDR11_CONFIG_MULTIBOOT_CORE_CONFIG_MULTIBOOT
S1W4:JCIBMUXOUTA0→ W14:JCIBMSPIMADDR12_CONFIG_MULTIBOOT_CORE_CONFIG_MULTIBOOT
S1W4:JCIBMUXOUTA1→ W14:JCIBMSPIMADDR13_CONFIG_MULTIBOOT_CORE_CONFIG_MULTIBOOT
S1W4:JCIBMUXOUTA2→ W14:JCIBMSPIMADDR14_CONFIG_MULTIBOOT_CORE_CONFIG_MULTIBOOT
S1W4:JCIBMUXOUTA3→ W14:JCIBMSPIMADDR15_CONFIG_MULTIBOOT_CORE_CONFIG_MULTIBOOT
S1W4:JCIBMUXOUTA4→ W14:JCIBMSPIMADDR16_CONFIG_MULTIBOOT_CORE_CONFIG_MULTIBOOT
S1W4:JCIBMUXOUTA5→ W14:JCIBMSPIMADDR17_CONFIG_MULTIBOOT_CORE_CONFIG_MULTIBOOT
S1W4:JCIBMUXOUTA6→ W14:JCIBMSPIMADDR18_CONFIG_MULTIBOOT_CORE_CONFIG_MULTIBOOT
S1W4:JCIBMUXOUTA7→ W14:JCIBMSPIMADDR19_CONFIG_MULTIBOOT_CORE_CONFIG_MULTIBOOT
S1W6:JCIBMUXOUTA2→ W14:JCIBMSPIMADDR1_CONFIG_MULTIBOOT_CORE_CONFIG_MULTIBOOT
S1W3:JCIBMUXOUTA1→ W14:JCIBMSPIMADDR20_CONFIG_MULTIBOOT_CORE_CONFIG_MULTIBOOT
S1W3:JCIBMUXOUTA3→ W14:JCIBMSPIMADDR21_CONFIG_MULTIBOOT_CORE_CONFIG_MULTIBOOT
S1W3:JCIBMUXOUTA4→ W14:JCIBMSPIMADDR22_CONFIG_MULTIBOOT_CORE_CONFIG_MULTIBOOT
S1W3:JCIBMUXOUTA6→ W14:JCIBMSPIMADDR23_CONFIG_MULTIBOOT_CORE_CONFIG_MULTIBOOT
S1W3:JCIBMUXOUTA7→ W14:JCIBMSPIMADDR24_CONFIG_MULTIBOOT_CORE_CONFIG_MULTIBOOT
S1W2:JCIBMUXOUTA0→ W14:JCIBMSPIMADDR25_CONFIG_MULTIBOOT_CORE_CONFIG_MULTIBOOT
S1W2:JCIBMUXOUTA1→ W14:JCIBMSPIMADDR26_CONFIG_MULTIBOOT_CORE_CONFIG_MULTIBOOT
S1W2:JCIBMUXOUTA2→ W14:JCIBMSPIMADDR27_CONFIG_MULTIBOOT_CORE_CONFIG_MULTIBOOT
S1W2:JCIBMUXOUTA3→ W14:JCIBMSPIMADDR28_CONFIG_MULTIBOOT_CORE_CONFIG_MULTIBOOT
S1W2:JCIBMUXOUTA4→ W14:JCIBMSPIMADDR29_CONFIG_MULTIBOOT_CORE_CONFIG_MULTIBOOT
S1W6:JCIBMUXOUTA3→ W14:JCIBMSPIMADDR2_CONFIG_MULTIBOOT_CORE_CONFIG_MULTIBOOT
S1W2:JCIBMUXOUTA5→ W14:JCIBMSPIMADDR30_CONFIG_MULTIBOOT_CORE_CONFIG_MULTIBOOT
S1W2:JCIBMUXOUTA6→ W14:JCIBMSPIMADDR31_CONFIG_MULTIBOOT_CORE_CONFIG_MULTIBOOT
S1W6:JCIBMUXOUTA4→ W14:JCIBMSPIMADDR3_CONFIG_MULTIBOOT_CORE_CONFIG_MULTIBOOT
S1W6:JCIBMUXOUTA5→ W14:JCIBMSPIMADDR4_CONFIG_MULTIBOOT_CORE_CONFIG_MULTIBOOT
S1W6:JCIBMUXOUTA6→ W14:JCIBMSPIMADDR5_CONFIG_MULTIBOOT_CORE_CONFIG_MULTIBOOT
S1W6:JCIBMUXOUTA7→ W14:JCIBMSPIMADDR6_CONFIG_MULTIBOOT_CORE_CONFIG_MULTIBOOT
S1W5:JCIBMUXOUTA1→ W14:JCIBMSPIMADDR7_CONFIG_MULTIBOOT_CORE_CONFIG_MULTIBOOT
S1W5:JCIBMUXOUTA3→ W14:JCIBMSPIMADDR8_CONFIG_MULTIBOOT_CORE_CONFIG_MULTIBOOT
S1W5:JCIBMUXOUTA4→ W14:JCIBMSPIMADDR9_CONFIG_MULTIBOOT_CORE_CONFIG_MULTIBOOT
S1W2:JCIBMUXOUTA7→ W14:JCIBTSALL_CONFIG_IP_CORE_CONFIG_IP
S1W4:JLSR0→ W14:JCRELRSTN_CONFIG_CRE_CORE_CONFIG_HSE
W14:JHSE_CLK_CONFIG_CLKRST_CORE_CONFIG_CLKRST→ W14:JCRE_CLK_CONFIG_CRE_CORE_CONFIG_HSE
S1E3:JLSR0→ W14:JJTAG_LRST_N_CONFIG_CLKRST_CORE_CONFIG_CLKRST
S1W11:JCLK0→ W14:JLMMICLK_CONFIG_CRE_CORE_CONFIG_HSE
W14:JLMMI_CLK_O_CONFIG_CLKRST_CORE_CONFIG_CLKRST→ W14:JLMMICLK_CONFIG_LMMI_CORE_LMMI_MODEL
S1W11:JCIBMUXOUTB0→ W14:JLMMIOFFSET0_CONFIG_CRE_CORE_CONFIG_HSE
S1E2:JCIBMUXOUTC0→ W14:JLMMIOFFSET0_CONFIG_LMMI_CORE_LMMI_MODEL
S1W8:JCIBMUXOUTB2→ W14:JLMMIOFFSET10_CONFIG_CRE_CORE_CONFIG_HSE
S1W8:JCIBMUXOUTB3→ W14:JLMMIOFFSET11_CONFIG_CRE_CORE_CONFIG_HSE
S1W8:JCIBMUXOUTB4→ W14:JLMMIOFFSET12_CONFIG_CRE_CORE_CONFIG_HSE
S1W8:JCIBMUXOUTB5→ W14:JLMMIOFFSET13_CONFIG_CRE_CORE_CONFIG_HSE
S1W8:JCIBMUXOUTB6→ W14:JLMMIOFFSET14_CONFIG_CRE_CORE_CONFIG_HSE
S1W8:JCIBMUXOUTB7→ W14:JLMMIOFFSET15_CONFIG_CRE_CORE_CONFIG_HSE
S1W10:JCIBMUXOUTB7→ W14:JLMMIOFFSET16_CONFIG_CRE_CORE_CONFIG_HSE
S1W9:JCIBMUXOUTB7→ W14:JLMMIOFFSET17_CONFIG_CRE_CORE_CONFIG_HSE
S1W11:JCIBMUXOUTB1→ W14:JLMMIOFFSET1_CONFIG_CRE_CORE_CONFIG_HSE
S1E2:JCIBMUXOUTC1→ W14:JLMMIOFFSET1_CONFIG_LMMI_CORE_LMMI_MODEL
S1W11:JCIBMUXOUTB2→ W14:JLMMIOFFSET2_CONFIG_CRE_CORE_CONFIG_HSE
S1E2:JCIBMUXOUTC2→ W14:JLMMIOFFSET2_CONFIG_LMMI_CORE_LMMI_MODEL
S1W11:JCIBMUXOUTB3→ W14:JLMMIOFFSET3_CONFIG_CRE_CORE_CONFIG_HSE
S1E2:JCIBMUXOUTC3→ W14:JLMMIOFFSET3_CONFIG_LMMI_CORE_LMMI_MODEL
S1W11:JCIBMUXOUTB4→ W14:JLMMIOFFSET4_CONFIG_CRE_CORE_CONFIG_HSE
S1E2:JCIBMUXOUTC4→ W14:JLMMIOFFSET4_CONFIG_LMMI_CORE_LMMI_MODEL
S1W11:JCIBMUXOUTB5→ W14:JLMMIOFFSET5_CONFIG_CRE_CORE_CONFIG_HSE
S1E2:JCIBMUXOUTC5→ W14:JLMMIOFFSET5_CONFIG_LMMI_CORE_LMMI_MODEL
S1W11:JCIBMUXOUTB6→ W14:JLMMIOFFSET6_CONFIG_CRE_CORE_CONFIG_HSE
S1E2:JCIBMUXOUTC6→ W14:JLMMIOFFSET6_CONFIG_LMMI_CORE_LMMI_MODEL
S1W11:JCIBMUXOUTB7→ W14:JLMMIOFFSET7_CONFIG_CRE_CORE_CONFIG_HSE
S1E2:JCIBMUXOUTC7→ W14:JLMMIOFFSET7_CONFIG_LMMI_CORE_LMMI_MODEL
S1W8:JCIBMUXOUTB0→ W14:JLMMIOFFSET8_CONFIG_CRE_CORE_CONFIG_HSE
S1W8:JCIBMUXOUTB1→ W14:JLMMIOFFSET9_CONFIG_CRE_CORE_CONFIG_HSE
S1W11:JCIBMUXOUTA0→ W14:JLMMIREQUEST_CONFIG_CRE_CORE_CONFIG_HSE
S1:JCIBMUXOUTA1→ W14:JLMMIREQUEST_CONFIG_LMMI_CORE_LMMI_MODEL
S1E2:JLSR0→ W14:JLMMIRESETN_CONFIG_CRE_CORE_CONFIG_HSE
W14:JLMMI_RST_CONFIG_CLKRST_CORE_CONFIG_CLKRST→ W14:JLMMIRESETN_CONFIG_LMMI_CORE_LMMI_MODEL
S1W12:JCIBMUXOUTA1→ W14:JLMMIWDATA0_CONFIG_CRE_CORE_CONFIG_HSE
S1W1:JCIBMUXOUTA4→ W14:JLMMIWDATA0_CONFIG_LMMI_CORE_LMMI_MODEL
S1W9:JCIBMUXOUTA3→ W14:JLMMIWDATA10_CONFIG_CRE_CORE_CONFIG_HSE
S1W9:JCIBMUXOUTA4→ W14:JLMMIWDATA11_CONFIG_CRE_CORE_CONFIG_HSE
S1W9:JCIBMUXOUTA6→ W14:JLMMIWDATA12_CONFIG_CRE_CORE_CONFIG_HSE
S1W9:JCIBMUXOUTA7→ W14:JLMMIWDATA13_CONFIG_CRE_CORE_CONFIG_HSE
S1W8:JCIBMUXOUTA0→ W14:JLMMIWDATA14_CONFIG_CRE_CORE_CONFIG_HSE
S1W8:JCIBMUXOUTA1→ W14:JLMMIWDATA15_CONFIG_CRE_CORE_CONFIG_HSE
S1W8:JCIBMUXOUTA2→ W14:JLMMIWDATA16_CONFIG_CRE_CORE_CONFIG_HSE
S1W8:JCIBMUXOUTA3→ W14:JLMMIWDATA17_CONFIG_CRE_CORE_CONFIG_HSE
S1W8:JCIBMUXOUTA4→ W14:JLMMIWDATA18_CONFIG_CRE_CORE_CONFIG_HSE
S1W8:JCIBMUXOUTA5→ W14:JLMMIWDATA19_CONFIG_CRE_CORE_CONFIG_HSE
S1W12:JCIBMUXOUTA2→ W14:JLMMIWDATA1_CONFIG_CRE_CORE_CONFIG_HSE
S1W1:JCIBMUXOUTA6→ W14:JLMMIWDATA1_CONFIG_LMMI_CORE_LMMI_MODEL
S1W8:JCIBMUXOUTA6→ W14:JLMMIWDATA20_CONFIG_CRE_CORE_CONFIG_HSE
S1W8:JCIBMUXOUTA7→ W14:JLMMIWDATA21_CONFIG_CRE_CORE_CONFIG_HSE
S1W7:JCIBMUXOUTA3→ W14:JLMMIWDATA22_CONFIG_CRE_CORE_CONFIG_HSE
S1W7:JCIBMUXOUTA1→ W14:JLMMIWDATA23_CONFIG_CRE_CORE_CONFIG_HSE
S1W7:JCIBMUXOUTA4→ W14:JLMMIWDATA24_CONFIG_CRE_CORE_CONFIG_HSE
S1W7:JCIBMUXOUTA6→ W14:JLMMIWDATA25_CONFIG_CRE_CORE_CONFIG_HSE
S1W7:JCIBMUXOUTA7→ W14:JLMMIWDATA26_CONFIG_CRE_CORE_CONFIG_HSE
S1W13:JCIBMUXOUTA5→ W14:JLMMIWDATA27_CONFIG_CRE_CORE_CONFIG_HSE
S1W13:JCIBMUXOUTA3→ W14:JLMMIWDATA28_CONFIG_CRE_CORE_CONFIG_HSE
S1W13:JCIBMUXOUTA0→ W14:JLMMIWDATA29_CONFIG_CRE_CORE_CONFIG_HSE
S1W12:JCIBMUXOUTA3→ W14:JLMMIWDATA2_CONFIG_CRE_CORE_CONFIG_HSE
S1:JCIBMUXOUTA2→ W14:JLMMIWDATA2_CONFIG_LMMI_CORE_LMMI_MODEL
S1W13:JCIBMUXOUTA6→ W14:JLMMIWDATA30_CONFIG_CRE_CORE_CONFIG_HSE
S1W13:JCIBMUXOUTA7→ W14:JLMMIWDATA31_CONFIG_CRE_CORE_CONFIG_HSE
S1W12:JCIBMUXOUTA4→ W14:JLMMIWDATA3_CONFIG_CRE_CORE_CONFIG_HSE
S1:JCIBMUXOUTA3→ W14:JLMMIWDATA3_CONFIG_LMMI_CORE_LMMI_MODEL
S1W12:JCIBMUXOUTA5→ W14:JLMMIWDATA4_CONFIG_CRE_CORE_CONFIG_HSE
S1:JCIBMUXOUTA4→ W14:JLMMIWDATA4_CONFIG_LMMI_CORE_LMMI_MODEL
S1W12:JCIBMUXOUTA6→ W14:JLMMIWDATA5_CONFIG_CRE_CORE_CONFIG_HSE
S1:JCIBMUXOUTA5→ W14:JLMMIWDATA5_CONFIG_LMMI_CORE_LMMI_MODEL
S1W11:JCIBMUXOUTA5→ W14:JLMMIWDATA6_CONFIG_CRE_CORE_CONFIG_HSE
S1:JCIBMUXOUTA6→ W14:JLMMIWDATA6_CONFIG_LMMI_CORE_LMMI_MODEL
S1W11:JCIBMUXOUTA6→ W14:JLMMIWDATA7_CONFIG_CRE_CORE_CONFIG_HSE
S1:JCIBMUXOUTA7→ W14:JLMMIWDATA7_CONFIG_LMMI_CORE_LMMI_MODEL
S1W11:JCIBMUXOUTA7→ W14:JLMMIWDATA8_CONFIG_CRE_CORE_CONFIG_HSE
S1W9:JCIBMUXOUTA1→ W14:JLMMIWDATA9_CONFIG_CRE_CORE_CONFIG_HSE
S1W11:JCIBMUXOUTA4→ W14:JLMMIWRRDN_CONFIG_CRE_CORE_CONFIG_HSE
S1E1:JCIBMUXOUTA7→ W14:JLMMIWRRDN_CONFIG_LMMI_CORE_LMMI_MODEL
S1W4:JCLK0→ W14:JLMMI_CLK_CONFIG_CLKRST_CORE_CONFIG_CLKRST
S1E3:JLSR1→ W14:JLMMI_LRST_N_CONFIG_CLKRST_CORE_CONFIG_CLKRST
S1E1:JCIBMUXOUTA4→ W14:JMBISTENABLEN_CONFIG_IP_CORE_CONFIG_IP
S1E1:JCIBMUXOUTA6→ W14:JMBISTTRRAEN_CONFIG_IP_CORE_CONFIG_IP
W14:JCFG_CLK_CONFIG_CLKRST_CORE_CONFIG_CLKRST→ W14:JOSCCLKSEDC_CONFIG_SEDC_CORE_CONFIG_SEDC
S1E5:JHFCLKCFG_OSC_CORE→ W14:JOSCCLK_CONFIG_CLKRST_CORE_CONFIG_CLKRST
S1:JCIBMUXOUTA0→ W14:JOTM_CONFIG_CRE_CORE_CONFIG_HSE
W14:JSEDC_RST_CONFIG_CLKRST_CORE_CONFIG_CLKRST→ W14:JRSTSEDC_CONFIG_SEDC_CORE_CONFIG_SEDC
W14:JSMCLK_RST_CONFIG_CLKRST_CORE_CONFIG_CLKRST→ W14:JRSTSMCLK_CONFIG_LMMI_CORE_LMMI_MODEL
S1E5:JHFSDCOUT_OSC_CORE→ W14:JSEDC_CLK_CONFIG_CLKRST_CORE_CONFIG_CLKRST
S1E5:JLSR0→ W14:JSEDC_LRST_N_CONFIG_CLKRST_CORE_CONFIG_CLKRST
W14:JCFG_CLK_CONFIG_CLKRST_CORE_CONFIG_CLKRST→ W14:JSMCLK_CONFIG_JTAG_CORE_CONFIG_JTAG
W14:JCFG_CLK_CONFIG_CLKRST_CORE_CONFIG_CLKRST→ W14:JSMCLK_CONFIG_LMMI_CORE_LMMI_MODEL
W14:JWDT_CLK_CONFIG_CLKRST_CORE_CONFIG_CLKRST→ W14:JWDT_CLK_CONFIG_WDT_CORE_CONFIG_WDT
S1E5:JLSR1→ W14:JWDT_LRST_N_CONFIG_CLKRST_CORE_CONFIG_CLKRST
W14:JWDT_RST_CONFIG_CLKRST_CORE_CONFIG_CLKRST→ W14:JWDT_RST_CONFIG_WDT_CORE_CONFIG_WDT