ECLK_3 Tile Documentation

Config Bitmap

 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
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Routing Muxes

Mux driving G:JECLKOUT1_ECLKCASMUX_CORE_ECLKCASMUX3

Source F20B0
N1W1:JECLKCAS1M1_ECLKCASMUX_CORE_ECLKCASMUX3 -
N1W1:JECLKCAS0M1_ECLKCASMUX_CORE_ECLKCASMUX3 1
N1W1:JECLKSYNCM1_ECLKCASMUX_CORE_ECLKCASMUX3 1

Mux driving G:JECLKOUT1_ECLKCASMUX_CORE_ECLKCASMUX4

Source F104B0 F105B0
N1W2:JECLKCAS0M1_ECLKCASMUX_CORE_ECLKCASMUX4 - 1
N1W2:JECLKCAS1M1_ECLKCASMUX_CORE_ECLKCASMUX4 1 -
N1W2:JECLKSYNCM1_ECLKCASMUX_CORE_ECLKCASMUX4 1 1

Mux driving G:JECLKOUT2_ECLKCASMUX_CORE_ECLKCASMUX3

Source F25B0 F26B0
N1W1:JECLKCAS0M2_ECLKCASMUX_CORE_ECLKCASMUX3 - 1
N1W1:JECLKCAS1M2_ECLKCASMUX_CORE_ECLKCASMUX3 1 -
N1W1:JECLKSYNCM2_ECLKCASMUX_CORE_ECLKCASMUX3 1 1

Mux driving G:JECLKOUT3_ECLKCASMUX_CORE_ECLKCASMUX3

Source F32B0 F33B0
N1W1:JECLKCAS0M3_ECLKCASMUX_CORE_ECLKCASMUX3 - 1
N1W1:JECLKCAS1M3_ECLKCASMUX_CORE_ECLKCASMUX3 1 -
N1W1:JECLKSYNCM3_ECLKCASMUX_CORE_ECLKCASMUX3 1 1

Mux driving G:JMUXIN1_ECLKBANK_CORE_ECLKBANK4

Source F100B0 F101B0 F102B0 F103B0
G:JPCLKT1_ECLKBANK_CORE_ECLKBANK4 - 1 - -
G:JLRCLKOS5_ECLKBANK_CORE_ECLKBANK4 - 1 - 1
G:JPCLKT0_ECLKBANK_CORE_ECLKBANK4 - 1 1 -
G:JLRCLKOS3_ECLKBANK_CORE_ECLKBANK4 - 1 1 1
G:JPCLKT3_ECLKBANK_CORE_ECLKBANK4 1 - - 1
N1W2:JECLKCIB1_ECLKBANK_CORE_ECLKBANK4 1 - 1 -
G:JPCLKT2_ECLKBANK_CORE_ECLKBANK4 1 - 1 1
G:JLRCLKOS2_ECLKBANK_CORE_ECLKBANK4 1 1 - -
G:JLLCLKOS_ECLKBANK_CORE_ECLKBANK4 1 1 - 1
G:JLLCLKOS4_ECLKBANK_CORE_ECLKBANK4 1 1 1 -
G:JLLCLKOP_ECLKBANK_CORE_ECLKBANK4 1 1 1 1

Mux driving G:JMUXIN2_ECLKBANK_CORE_ECLKBANK3

Source F21B0 F22B0 F23B0 F24B0
G:JPCLKT1_ECLKBANK_CORE_ECLKBANK3 - 1 - -
G:JLRCLKOS4_ECLKBANK_CORE_ECLKBANK3 - 1 - 1
G:JPCLKT0_ECLKBANK_CORE_ECLKBANK3 - 1 1 -
G:JLRCLKOS3_ECLKBANK_CORE_ECLKBANK3 - 1 1 1
G:JPCLKT3_ECLKBANK_CORE_ECLKBANK3 1 - - 1
N1W1:JECLKCIB2_ECLKBANK_CORE_ECLKBANK3 1 - 1 -
G:JPCLKT2_ECLKBANK_CORE_ECLKBANK3 1 - 1 1
G:JLRCLKOP_ECLKBANK_CORE_ECLKBANK3 1 1 - -
G:JLLCLKOS2_ECLKBANK_CORE_ECLKBANK3 1 1 - 1
G:JLLCLKOS5_ECLKBANK_CORE_ECLKBANK3 1 1 1 -
G:JLLCLKOS_ECLKBANK_CORE_ECLKBANK3 1 1 1 1

Mux driving G:JMUXIN3_ECLKBANK_CORE_ECLKBANK3

Source F27B0 F28B0 F29B0 F31B0
G:JPCLKT1_ECLKBANK_CORE_ECLKBANK3 - 1 - -
G:JLRCLKOS5_ECLKBANK_CORE_ECLKBANK3 - 1 - 1
G:JPCLKT0_ECLKBANK_CORE_ECLKBANK3 - 1 1 -
G:JLRCLKOS_ECLKBANK_CORE_ECLKBANK3 - 1 1 1
G:JPCLKT3_ECLKBANK_CORE_ECLKBANK3 1 - - 1
N1W1:JECLKCIB3_ECLKBANK_CORE_ECLKBANK3 1 - 1 -
G:JPCLKT2_ECLKBANK_CORE_ECLKBANK3 1 - 1 1
G:JLRCLKOP_ECLKBANK_CORE_ECLKBANK3 1 1 - -
G:JLLCLKOS3_ECLKBANK_CORE_ECLKBANK3 1 1 - 1
G:JLLCLKOS4_ECLKBANK_CORE_ECLKBANK3 1 1 1 -
G:JLLCLKOS2_ECLKBANK_CORE_ECLKBANK3 1 1 1 1

Fixed Connections

SourceSink
N1:JCIBMUXOUTB7→ N1:JTESTINP0_ECLKLOGICMUXPLLFB_CORE_ECLKPLLFBR
N1:JCIBMUXOUTB6→ N1:JTESTINP1_ECLKLOGICMUXPLLFB_CORE_ECLKPLLFBR
N1:JCIBMUXOUTB4→ N1:JTESTINP2_ECLKLOGICMUXPLLFB_CORE_ECLKPLLFBR
N1:JCIBMUXOUTB5→ N1:JTESTINP3_ECLKLOGICMUXPLLFB_CORE_ECLKPLLFBR