ECLK_0 Tile Documentation

Config Bitmap

 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
E
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E
 
E
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E
E
E
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

Routing Muxes

Mux driving G:JECLKOUT2_ECLKCASMUX_CORE_ECLKCASMUX4

Source F80B0 F81B0
N1E1:JECLKCAS0M2_ECLKCASMUX_CORE_ECLKCASMUX4 - 1
N1E1:JECLKCAS1M2_ECLKCASMUX_CORE_ECLKCASMUX4 1 -
N1E1:JECLKSYNCM2_ECLKCASMUX_CORE_ECLKCASMUX4 1 1

Mux driving G:JECLKOUT2_ECLKCASMUX_CORE_ECLKCASMUX5

Source F93B0
N1:JECLKCAS0M2_ECLKCASMUX_CORE_ECLKCASMUX5 -
N1:JECLKCAS1M2_ECLKCASMUX_CORE_ECLKCASMUX5 1
N1:JECLKSYNCM2_ECLKCASMUX_CORE_ECLKCASMUX5 1

Mux driving G:JMUXIN2_ECLKBANK_CORE_ECLKBANK5

Source F88B0 F89B0 F91B0 F92B0
G:JPCLKT1_ECLKBANK_CORE_ECLKBANK5 - 1 - -
G:JLRCLKOS4_ECLKBANK_CORE_ECLKBANK5 - 1 - 1
G:JPCLKT0_ECLKBANK_CORE_ECLKBANK5 - 1 1 -
G:JLRCLKOS3_ECLKBANK_CORE_ECLKBANK5 - 1 1 1
G:JPCLKT3_ECLKBANK_CORE_ECLKBANK5 1 - - 1
N1:JECLKCIB2_ECLKBANK_CORE_ECLKBANK5 1 - 1 -
G:JPCLKT2_ECLKBANK_CORE_ECLKBANK5 1 - 1 1
G:JLRCLKOP_ECLKBANK_CORE_ECLKBANK5 1 1 - -
G:JLLCLKOS2_ECLKBANK_CORE_ECLKBANK5 1 1 - 1
G:JLLCLKOS5_ECLKBANK_CORE_ECLKBANK5 1 1 1 -
G:JLLCLKOS_ECLKBANK_CORE_ECLKBANK5 1 1 1 1

Mux driving G:JMUXIN3_ECLKBANK_CORE_ECLKBANK4

Source F82B0 F83B0 F84B0 F86B0
G:JPCLKT1_ECLKBANK_CORE_ECLKBANK4 - 1 - -
G:JLRCLKOS5_ECLKBANK_CORE_ECLKBANK4 - 1 - 1
G:JPCLKT0_ECLKBANK_CORE_ECLKBANK4 - 1 1 -
G:JLRCLKOS_ECLKBANK_CORE_ECLKBANK4 - 1 1 1
G:JPCLKT3_ECLKBANK_CORE_ECLKBANK4 1 - - 1
N1E1:JECLKCIB3_ECLKBANK_CORE_ECLKBANK4 1 - 1 -
G:JPCLKT2_ECLKBANK_CORE_ECLKBANK4 1 - 1 1
G:JLRCLKOP_ECLKBANK_CORE_ECLKBANK4 1 1 - -
G:JLLCLKOS3_ECLKBANK_CORE_ECLKBANK4 1 1 - 1
G:JLLCLKOS4_ECLKBANK_CORE_ECLKBANK4 1 1 1 -
G:JLLCLKOS2_ECLKBANK_CORE_ECLKBANK4 1 1 1 1

Fixed Connections

SourceSink
N1:JDIVOUT_ECLKDIV_CORE_ECLKDIVB5_2 G:JECLKDIV10_BMID_CORE_BMIDMUX
N1:JDIVOUT_ECLKDIV_CORE_ECLKDIVB5_3 G:JECLKDIV11_BMID_CORE_BMIDMUX
N1:JDIVOUT_ECLKDIV_CORE_ECLKDIVB5_0 G:JECLKDIV8_BMID_CORE_BMIDMUX
N1:JDIVOUT_ECLKDIV_CORE_ECLKDIVB5_1 G:JECLKDIV9_BMID_CORE_BMIDMUX
N1W4:JCLKOUT_DLLDEL_CORE_I0 G:JPCLKT0_ECLKBANK_CORE_ECLKBANK5
N1W3:JCLKOUT_DLLDEL_CORE_I0 G:JPCLKT2_ECLKBANK_CORE_ECLKBANK5
N1E1:JLSR0 N1:JDIVRST_ECLKDIV_CORE_ECLKDIVB5_0
N1E1:JLSR1 N1:JDIVRST_ECLKDIV_CORE_ECLKDIVB5_1
N1:JLSR0 N1:JDIVRST_ECLKDIV_CORE_ECLKDIVB5_2
N1:JLSR1 N1:JDIVRST_ECLKDIV_CORE_ECLKDIVB5_3
N1E1:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC4_0 N1:JECLKCAS0M0_ECLKCASMUX_CORE_ECLKCASMUX5
N1E1:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC4_1 N1:JECLKCAS0M1_ECLKCASMUX_CORE_ECLKCASMUX5
N1E1:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC4_2 N1:JECLKCAS0M2_ECLKCASMUX_CORE_ECLKCASMUX5
N1E1:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC4_3 N1:JECLKCAS0M3_ECLKCASMUX_CORE_ECLKCASMUX5
N1E2:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC3_0 N1:JECLKCAS1M0_ECLKCASMUX_CORE_ECLKCASMUX5
N1E2:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC3_1 N1:JECLKCAS1M1_ECLKCASMUX_CORE_ECLKCASMUX5
N1E2:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC3_2 N1:JECLKCAS1M2_ECLKCASMUX_CORE_ECLKCASMUX5
N1E2:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC3_3 N1:JECLKCAS1M3_ECLKCASMUX_CORE_ECLKCASMUX5
N1E1:JCIBMUXOUTD0 N1:JECLKCIB0_ECLKBANK_CORE_ECLKBANK5
N1E1:JCIBMUXOUTD1 N1:JECLKCIB1_ECLKBANK_CORE_ECLKBANK5
N1E1:JCIBMUXOUTD2 N1:JECLKCIB2_ECLKBANK_CORE_ECLKBANK5
N1E1:JCIBMUXOUTD3 N1:JECLKCIB3_ECLKBANK_CORE_ECLKBANK5
G:JECLKOUT0_ECLKCASMUX_CORE_ECLKCASMUX5 N1:JECLKIN_ECLKDIV_CORE_ECLKDIVB5_0
G:JECLKOUT1_ECLKCASMUX_CORE_ECLKCASMUX5 N1:JECLKIN_ECLKDIV_CORE_ECLKDIVB5_1
G:JECLKOUT2_ECLKCASMUX_CORE_ECLKCASMUX5 N1:JECLKIN_ECLKDIV_CORE_ECLKDIVB5_2
G:JECLKOUT3_ECLKCASMUX_CORE_ECLKCASMUX5 N1:JECLKIN_ECLKDIV_CORE_ECLKDIVB5_3
G:JMUXIN0_ECLKBANK_CORE_ECLKBANK5 N1:JECLKIN_ECLKSYNC_CORE_ECLKSYNC5_0
G:JMUXIN1_ECLKBANK_CORE_ECLKBANK5 N1:JECLKIN_ECLKSYNC_CORE_ECLKSYNC5_1
G:JMUXIN2_ECLKBANK_CORE_ECLKBANK5 N1:JECLKIN_ECLKSYNC_CORE_ECLKSYNC5_2
G:JMUXIN3_ECLKBANK_CORE_ECLKBANK5 N1:JECLKIN_ECLKSYNC_CORE_ECLKSYNC5_3
N1:JECLKIN_ECLKSYNC_CORE_ECLKSYNC5_0 N1:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC5_0
N1:JECLKIN_ECLKSYNC_CORE_ECLKSYNC5_1 N1:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC5_1
N1:JECLKIN_ECLKSYNC_CORE_ECLKSYNC5_2 N1:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC5_2
N1:JECLKIN_ECLKSYNC_CORE_ECLKSYNC5_3 N1:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC5_3
N1:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC5_0 N1:JECLKSYNCM0_ECLKCASMUX_CORE_ECLKCASMUX5
N1:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC5_1 N1:JECLKSYNCM1_ECLKCASMUX_CORE_ECLKCASMUX5
N1:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC5_2 N1:JECLKSYNCM2_ECLKCASMUX_CORE_ECLKCASMUX5
N1:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC5_3 N1:JECLKSYNCM3_ECLKCASMUX_CORE_ECLKCASMUX5
G:JECLKOUT0_ECLKCASMUX_CORE_ECLKCASMUX5 N1:JECLKTREE0_ECLKDDRL_0
G:JECLKOUT1_ECLKCASMUX_CORE_ECLKCASMUX5 N1:JECLKTREE0_ECLKDDRL_1
G:JECLKOUT2_ECLKCASMUX_CORE_ECLKCASMUX5 N1:JECLKTREE0_ECLKDDRL_2
G:JECLKOUT3_ECLKCASMUX_CORE_ECLKCASMUX5 N1:JECLKTREE0_ECLKDDRL_3
G:JECLKOUT0_ECLKCASMUX_CORE_ECLKCASMUX4 N1:JECLKTREE1_ECLKDDRL_0
G:JECLKOUT1_ECLKCASMUX_CORE_ECLKCASMUX4 N1:JECLKTREE1_ECLKDDRL_1
G:JECLKOUT2_ECLKCASMUX_CORE_ECLKCASMUX4 N1:JECLKTREE1_ECLKDDRL_2
G:JECLKOUT3_ECLKCASMUX_CORE_ECLKCASMUX4 N1:JECLKTREE1_ECLKDDRL_3
N1E3:JCIBMUXOUTD2 N1:JSLIP_ECLKDIV_CORE_ECLKDIVB5_0
N1E3:JCIBMUXOUTD3 N1:JSLIP_ECLKDIV_CORE_ECLKDIVB5_1
N1E3:JCIBMUXOUTD4 N1:JSLIP_ECLKDIV_CORE_ECLKDIVB5_2
N1E3:JCIBMUXOUTD5 N1:JSLIP_ECLKDIV_CORE_ECLKDIVB5_3
N1E2:JCIBMUXOUTD1 N1:JSTOP_ECLKSYNC_CORE_ECLKSYNC5_0
N1E2:JCIBMUXOUTB3 N1:JSTOP_ECLKSYNC_CORE_ECLKSYNC5_1
N1E2:JCIBMUXOUTD0 N1:JSTOP_ECLKSYNC_CORE_ECLKSYNC5_2
N1E2:JCIBMUXOUTB0 N1:JSTOP_ECLKSYNC_CORE_ECLKSYNC5_3
N1:JCIBMUXOUTB4 N1:JTESTINP0_ECLKBANK_CORE_ECLKBANK5
N1:JCIBMUXOUTC0 N1:JTESTINP0_ECLKCASMUX_CORE_ECLKCASMUX5
N1:JCIBMUXOUTD2 N1:JTESTINP0_ECLKDIV_CORE_ECLKDIVB5_0
N1:JCIBMUXOUTD2 N1:JTESTINP0_ECLKDIV_CORE_ECLKDIVB5_1
N1:JCIBMUXOUTD2 N1:JTESTINP0_ECLKDIV_CORE_ECLKDIVB5_2
N1:JCIBMUXOUTD2 N1:JTESTINP0_ECLKDIV_CORE_ECLKDIVB5_3
N1:JCIBMUXOUTB5 N1:JTESTINP1_ECLKBANK_CORE_ECLKBANK5
N1:JCIBMUXOUTC1 N1:JTESTINP1_ECLKCASMUX_CORE_ECLKCASMUX5
N1:JCIBMUXOUTD3 N1:JTESTINP1_ECLKDIV_CORE_ECLKDIVB5_0
N1:JCIBMUXOUTD3 N1:JTESTINP1_ECLKDIV_CORE_ECLKDIVB5_1
N1:JCIBMUXOUTD3 N1:JTESTINP1_ECLKDIV_CORE_ECLKDIVB5_2
N1:JCIBMUXOUTD3 N1:JTESTINP1_ECLKDIV_CORE_ECLKDIVB5_3
N1:JCIBMUXOUTB6 N1:JTESTINP2_ECLKBANK_CORE_ECLKBANK5
N1:JCIBMUXOUTD4 N1:JTESTINP2_ECLKDIV_CORE_ECLKDIVB5_0
N1:JCIBMUXOUTD4 N1:JTESTINP2_ECLKDIV_CORE_ECLKDIVB5_1
N1:JCIBMUXOUTD4 N1:JTESTINP2_ECLKDIV_CORE_ECLKDIVB5_2
N1:JCIBMUXOUTD4 N1:JTESTINP2_ECLKDIV_CORE_ECLKDIVB5_3
N1:JCIBMUXOUTB7 N1:JTESTINP3_ECLKBANK_CORE_ECLKBANK5
N1:JCIBMUXOUTD5 N1:JTESTINP3_ECLKDIV_CORE_ECLKDIVB5_0
N1:JCIBMUXOUTD5 N1:JTESTINP3_ECLKDIV_CORE_ECLKDIVB5_1
N1:JCIBMUXOUTD5 N1:JTESTINP3_ECLKDIV_CORE_ECLKDIVB5_2
N1:JCIBMUXOUTD5 N1:JTESTINP3_ECLKDIV_CORE_ECLKDIVB5_3
N1:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC5_0 N1E1:JECLKCAS1M0_ECLKCASMUX_CORE_ECLKCASMUX4
N1:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC5_1 N1E1:JECLKCAS1M1_ECLKCASMUX_CORE_ECLKCASMUX4
N1:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC5_2 N1E1:JECLKCAS1M2_ECLKCASMUX_CORE_ECLKCASMUX4
N1:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC5_3 N1E1:JECLKCAS1M3_ECLKCASMUX_CORE_ECLKCASMUX4
N1:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC5_0 N1E2:JECLKCAS0M0_ECLKCASMUX_CORE_ECLKCASMUX3
N1:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC5_1 N1E2:JECLKCAS0M1_ECLKCASMUX_CORE_ECLKCASMUX3
N1:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC5_2 N1E2:JECLKCAS0M2_ECLKCASMUX_CORE_ECLKCASMUX3
N1:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC5_3 N1E2:JECLKCAS0M3_ECLKCASMUX_CORE_ECLKCASMUX3