EBR_9 Tile Documentation

Tile Bels

NameType
EBR3 OXIDE_EBR

Config Bitmap

 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
F
 
E
W
F
 
 
 
F
W
 
C
 
C
C
W
R
1
E
C
E
W
E
W
E
W
E
W
E
W
E
W
E
W
E
W
E
W
F
W
F
R
F
W
F
R
 
F
 
F
 
F
 
F
M
F
E
 
 
F
E
F
E
F
E
F
E

Configuration Words

Configuration word EBR3.DP16K_MODE.CSDECODE_B

port is enabled when CS inputs match this value

EBR3.DP16K_MODE.CSDECODE_B[0]
EBR3.DP16K_MODE.CSDECODE_B[1]F53B0
EBR3.DP16K_MODE.CSDECODE_B[2]F52B0

Configuration word EBR3.FIFO16K_MODE.ALMOST_EMPTY

FIFO 'almost empty' output threshold

EBR3.FIFO16K_MODE.ALMOST_EMPTY[0]
EBR3.FIFO16K_MODE.ALMOST_EMPTY[1]
EBR3.FIFO16K_MODE.ALMOST_EMPTY[2]
EBR3.FIFO16K_MODE.ALMOST_EMPTY[3]F57B0
EBR3.FIFO16K_MODE.ALMOST_EMPTY[4]F59B0
EBR3.FIFO16K_MODE.ALMOST_EMPTY[5]F61B0
EBR3.FIFO16K_MODE.ALMOST_EMPTY[6]F63B0
EBR3.FIFO16K_MODE.ALMOST_EMPTY[7]F65B0
EBR3.FIFO16K_MODE.ALMOST_EMPTY[8]F67B0
EBR3.FIFO16K_MODE.ALMOST_EMPTY[9]F69B0
EBR3.FIFO16K_MODE.ALMOST_EMPTY[10]F71B0
EBR3.FIFO16K_MODE.ALMOST_EMPTY[11]F73B0
EBR3.FIFO16K_MODE.ALMOST_EMPTY[12]F75B0
EBR3.FIFO16K_MODE.ALMOST_EMPTY[13]F41B0

Configuration word EBR3.FIFO16K_MODE.ALMOST_FULL

FIFO 'almost full' output threshold

EBR3.FIFO16K_MODE.ALMOST_FULL[0]F77B0
EBR3.FIFO16K_MODE.ALMOST_FULL[1]F79B0
EBR3.FIFO16K_MODE.ALMOST_FULL[2]F81B0
EBR3.FIFO16K_MODE.ALMOST_FULL[3]F83B0
EBR3.FIFO16K_MODE.ALMOST_FULL[4]F86B0
EBR3.FIFO16K_MODE.ALMOST_FULL[5]F88B0
EBR3.FIFO16K_MODE.ALMOST_FULL[6]F90B0
EBR3.FIFO16K_MODE.ALMOST_FULL[7]F39B0
EBR3.FIFO16K_MODE.ALMOST_FULL[8]F43B0
EBR3.FIFO16K_MODE.ALMOST_FULL[9]F92B0
EBR3.FIFO16K_MODE.ALMOST_FULL[10]F94B0
EBR3.FIFO16K_MODE.ALMOST_FULL[11]F98B0
EBR3.FIFO16K_MODE.ALMOST_FULL[12]F100B0
EBR3.FIFO16K_MODE.ALMOST_FULL[13]F102B0

Configuration word EBR3.FIFO16K_MODE.EMPTYBITS

FIFO 'empty' threshold

EBR3.FIFO16K_MODE.EMPTYBITS[0]F95B0
EBR3.FIFO16K_MODE.EMPTYBITS[1]F99B0
EBR3.FIFO16K_MODE.EMPTYBITS[2]F101B0
EBR3.FIFO16K_MODE.EMPTYBITS[3]F103B0
EBR3.FIFO16K_MODE.EMPTYBITS[4]F105B0

Configuration word EBR3.FIFO16K_MODE.FULLBITS

FIFO 'full' threshold

EBR3.FIFO16K_MODE.FULLBITS[0]
EBR3.FIFO16K_MODE.FULLBITS[1]
EBR3.FIFO16K_MODE.FULLBITS[2]
EBR3.FIFO16K_MODE.FULLBITS[3]
EBR3.FIFO16K_MODE.FULLBITS[4]F47B0
EBR3.FIFO16K_MODE.FULLBITS[5]
EBR3.FIFO16K_MODE.FULLBITS[6]F104B0
EBR3.FIFO16K_MODE.FULLBITS[7]
EBR3.FIFO16K_MODE.FULLBITS[8]
EBR3.FIFO16K_MODE.FULLBITS[9]
EBR3.FIFO16K_MODE.FULLBITS[10]
EBR3.FIFO16K_MODE.FULLBITS[11]
EBR3.FIFO16K_MODE.FULLBITS[12]
EBR3.FIFO16K_MODE.FULLBITS[13]

Configuration word EBR3.PDP16K_MODE.CSDECODE_R

port is enabled when CS inputs match this value

EBR3.PDP16K_MODE.CSDECODE_R[0]
EBR3.PDP16K_MODE.CSDECODE_R[1]F53B0
EBR3.PDP16K_MODE.CSDECODE_R[2]F52B0

Configuration word EBR3.PDPSC16K_MODE.CSDECODE_R

port is enabled when CS inputs match this value

EBR3.PDPSC16K_MODE.CSDECODE_R[0]
EBR3.PDPSC16K_MODE.CSDECODE_R[1]F53B0
EBR3.PDPSC16K_MODE.CSDECODE_R[2]F52B0

Configuration word EBR3.SP16K_MODE.CSDECODE

port is enabled when CS inputs match this value

EBR3.SP16K_MODE.CSDECODE[0]
EBR3.SP16K_MODE.CSDECODE[1]F53B0
EBR3.SP16K_MODE.CSDECODE[2]F52B0

Configuration word EBR3.WID

unique ID for the BRAM, used to initialise it in the bitstream

EBR3.WID[0]F60B0
EBR3.WID[1]F62B0
EBR3.WID[2]F64B0
EBR3.WID[3]F66B0
EBR3.WID[4]F68B0
EBR3.WID[5]F70B0
EBR3.WID[6]F72B0
EBR3.WID[7]F74B0
EBR3.WID[8]F76B0
EBR3.WID[9]F42B0
EBR3.WID[10]F78B0

Configuration Enums

Configuration enum EBR3.DP16K_MODE.ASYNC_RST_RELEASE_A

Value F55B0
ASYNC 1
SYNC -

Configuration enum EBR3.DP16K_MODE.ASYNC_RST_RELEASE_B

Value F84B0
ASYNC 1
SYNC -

Configuration enum EBR3.DP16K_MODE.CEAMUX

Value F58B0
CEA -
INV 1

Configuration enum EBR3.DP16K_MODE.CEBMUX

Value F50B0
CEB -
INV 1

Configuration enum EBR3.DP16K_MODE.DATA_WIDTH_B

data width of port B in DP16K_MODE

Value F48B0
X1 1
X18 -
X2 1
X4 1
X9 -

Configuration enum EBR3.DP16K_MODE.RSTAMUX

Value F80B0
INV 1
RSTA -

Configuration enum EBR3.DP16K_MODE.WEBMUX

Value F82B0
INV 1
WEB -

Configuration enum EBR3.FIFO16K_MODE.ASYNC_RST_RELEASE_A

Value F55B0
ASYNC 1
SYNC -

Configuration enum EBR3.FIFO16K_MODE.ASYNC_RST_RELEASE_B

Value F84B0
ASYNC 1
SYNC -

Configuration enum EBR3.FIFO16K_MODE.CEAMUX

Value F58B0
CEA -
INV 1

Configuration enum EBR3.FIFO16K_MODE.CEBMUX

Value F50B0
CEB -
INV 1

Configuration enum EBR3.FIFO16K_MODE.DATA_WIDTH_A

data width of port A in FIFO16K_MODE

Value F54B0
X1 1
X18 1
X2 1
X32 -
X36 -
X4 1
X9 1

Configuration enum EBR3.FIFO16K_MODE.DATA_WIDTH_B

data width of port B in FIFO16K_MODE

Value F48B0
X1 1
X18 -
X2 1
X32 -
X36 -
X4 1
X9 -

Configuration enum EBR3.FIFO16K_MODE.RSTAMUX

Value F80B0
INV 1
RSTA -

Configuration enum EBR3.MODE

EBR3 primitive mode

Value F54B0 F82B0 F93B0
DP16K_MODE 1 - -
FIFO16K_MODE - 1 -
NONE - - -
PDP16K_MODE - 1 -
PDPSC16K_MODE - 1 1
SP16K_MODE 1 - 1

Configuration enum EBR3.PDP16K_MODE.ASYNC_RST_RELEASE

Value F55B0 F84B0
ASYNC 1 1
SYNC - -

Configuration enum EBR3.PDP16K_MODE.CERMUX

Value F50B0
CER -
INV 1

Configuration enum EBR3.PDP16K_MODE.CEWMUX

Value F58B0
CEW -
INV 1

Configuration enum EBR3.PDP16K_MODE.DATA_WIDTH_R

data width of read port in PDP16K_MODE

Value F48B0
X1 1
X18 -
X2 1
X32 -
X36 -
X4 1
X9 -

Configuration enum EBR3.PDP16K_MODE.DATA_WIDTH_W

data width of write port in PDP16K_MODE

Value F54B0
X1 1
X18 1
X2 1
X32 -
X36 -
X4 1
X9 1

Configuration enum EBR3.PDP16K_MODE.RSTMUX

Value F80B0
INV 1
RST -

Configuration enum EBR3.PDPSC16K_MODE.ASYNC_RST_RELEASE

Value F55B0 F84B0
ASYNC 1 1
SYNC - -

Configuration enum EBR3.PDPSC16K_MODE.CERMUX

Value F50B0
CER -
INV 1

Configuration enum EBR3.PDPSC16K_MODE.CEWMUX

Value F58B0
CEW -
INV 1

Configuration enum EBR3.PDPSC16K_MODE.DATA_WIDTH_R

data width of read port in PDPSC16K_MODE

Value F48B0
X1 1
X18 -
X2 1
X32 -
X36 -
X4 1
X9 -

Configuration enum EBR3.PDPSC16K_MODE.DATA_WIDTH_W

data width of write port in PDPSC16K_MODE

Value F54B0
X1 1
X18 1
X2 1
X32 -
X36 -
X4 1
X9 1

Configuration enum EBR3.PDPSC16K_MODE.RSTMUX

Value F80B0
INV 1
RST -

Configuration enum EBR3.SP16K_MODE.ASYNC_RST_RELEASE

Value F55B0 F84B0
ASYNC 1 1
SYNC - -

Configuration enum EBR3.SP16K_MODE.CEMUX

Value F50B0 F58B0
CE - -
INV 1 1

Configuration enum EBR3.SP16K_MODE.DATA_WIDTH

data width of R/W port in SP16K_MODE

Value F48B0
X1 1
X18 -
X2 1
X4 1
X9 -

Configuration enum EBR3.SP16K_MODE.RSTMUX

Value F80B0
INV 1
RST -

Configuration enum EBR3.SP16K_MODE.WEMUX

Value F82B0
INV 1
WE -

Fixed Connections

SourceSink
N1W1:JDOA2_EBR_CORE→ N1:JF0
N1W1:JDOA3_EBR_CORE→ N1:JF1
N1W1:JDOA4_EBR_CORE→ N1:JF2
N1W1:JDOA5_EBR_CORE→ N1:JF3
N1W1:JDOA6_EBR_CORE→ N1:JF4
N1W1:JDOA7_EBR_CORE→ N1:JF5
N1W1:JDOA8_EBR_CORE→ N1:JF6
N1W1:JDOA9_EBR_CORE→ N1:JF7
N1W1:JDOB2_EBR_CORE→ N1:JQ0
N1W1:JDOB3_EBR_CORE→ N1:JQ1
N1W1:JDOB4_EBR_CORE→ N1:JQ2
N1W1:JDOB5_EBR_CORE→ N1:JQ3
N1W1:JDOB6_EBR_CORE→ N1:JQ4
N1W1:JDOB7_EBR_CORE→ N1:JQ5
N1W1:JDOB8_EBR_CORE→ N1:JQ6
N1W1:JDOB9_EBR_CORE→ N1:JQ7
N1W1:JDOA10_EBR_CORE→ N1E1:JF0
N1W1:JDOA11_EBR_CORE→ N1E1:JF1
N1W1:JDOA12_EBR_CORE→ N1E1:JF2
N1W1:JDOA13_EBR_CORE→ N1E1:JF3
N1W1:JDOA14_EBR_CORE→ N1E1:JF4
N1W1:JDOA15_EBR_CORE→ N1E1:JF5
N1W1:JDOA16_EBR_CORE→ N1E1:JF6
N1W1:JDOA17_EBR_CORE→ N1E1:JF7
N1W1:JDOB10_EBR_CORE→ N1E1:JQ0
N1W1:JDOB11_EBR_CORE→ N1E1:JQ1
N1W1:JDOB12_EBR_CORE→ N1E1:JQ2
N1W1:JDOB13_EBR_CORE→ N1E1:JQ3
N1W1:JDOB14_EBR_CORE→ N1E1:JQ4
N1W1:JDOB15_EBR_CORE→ N1E1:JQ5
N1W1:JDOB16_EBR_CORE→ N1E1:JQ6
N1W1:JDOB17_EBR_CORE→ N1E1:JQ7
N1E1:JCIBMUXOUTA3→ N1W1:JADA0_EBR_CORE
N1W1:JCIBMUXOUTD7→ N1W1:JADA10_EBR_CORE
N1W1:JCIBMUXOUTA5→ N1W1:JADA11_EBR_CORE
N1W1:JCIBMUXOUTC7→ N1W1:JADA12_EBR_CORE
N1W1:JCIBMUXOUTB3→ N1W1:JADA13_EBR_CORE
N1E1:JCIBMUXOUTA5→ N1W1:JADA1_EBR_CORE
N1E1:JCIBMUXOUTB1→ N1W1:JADA2_EBR_CORE
N1E1:JCIBMUXOUTB5→ N1W1:JADA3_EBR_CORE
N1W1:JCIBMUXOUTD2→ N1W1:JADA4_EBR_CORE
N1W1:JCIBMUXOUTB2→ N1W1:JADA5_EBR_CORE
N1W1:JCIBMUXOUTD6→ N1W1:JADA6_EBR_CORE
N1W1:JCIBMUXOUTB7→ N1W1:JADA7_EBR_CORE
N1W1:JCIBMUXOUTD1→ N1W1:JADA8_EBR_CORE
N1W1:JCIBMUXOUTA1→ N1W1:JADA9_EBR_CORE
N1E1:JCIBMUXOUTC6→ N1W1:JADB0_EBR_CORE
N1:JCIBMUXOUTD7→ N1W1:JADB10_EBR_CORE
N1W1:JCIBMUXOUTA7→ N1W1:JADB11_EBR_CORE
N1E1:JCIBMUXOUTD6→ N1W1:JADB12_EBR_CORE
N1E1:JCIBMUXOUTB3→ N1W1:JADB13_EBR_CORE
N1E1:JCIBMUXOUTC7→ N1W1:JADB1_EBR_CORE
N1E1:JCIBMUXOUTD0→ N1W1:JADB2_EBR_CORE
N1E1:JCIBMUXOUTD1→ N1W1:JADB3_EBR_CORE
N1:JCIBMUXOUTD0→ N1W1:JADB4_EBR_CORE
N1:JCIBMUXOUTB3→ N1W1:JADB5_EBR_CORE
N1:JCIBMUXOUTD6→ N1W1:JADB6_EBR_CORE
N1W1:JCIBMUXOUTB5→ N1W1:JADB7_EBR_CORE
N1:JCIBMUXOUTD1→ N1W1:JADB8_EBR_CORE
N1W1:JCIBMUXOUTA3→ N1W1:JADB9_EBR_CORE
N1:JCE0→ N1W1:JCEA_EBR_CORE
N1E1:JCE0→ N1W1:JCEB_EBR_CORE
N1E1:JCLK0→ N1W1:JCLKA_EBR_CORE
N1E1:JCLK1→ N1W1:JCLKB_EBR_CORE
N1:JCE1→ N1W1:JCSA0_EBR_CORE
N1:JCLK0→ N1W1:JCSA1_EBR_CORE
N1W1:JCE0→ N1W1:JCSA2_EBR_CORE
N1E1:JCE1→ N1W1:JCSB0_EBR_CORE
N1:JCLK1→ N1W1:JCSB1_EBR_CORE
N1W1:JLSR0→ N1W1:JCSB2_EBR_CORE
N1W1:JCIBMUXOUTA6→ N1W1:JDIA0_EBR_CORE
N1E1:JCIBMUXOUTB0→ N1W1:JDIA10_EBR_CORE
N1E1:JCIBMUXOUTA0→ N1W1:JDIA11_EBR_CORE
N1E1:JCIBMUXOUTB2→ N1W1:JDIA12_EBR_CORE
N1E1:JCIBMUXOUTA2→ N1W1:JDIA13_EBR_CORE
N1E1:JCIBMUXOUTA4→ N1W1:JDIA14_EBR_CORE
N1E1:JCIBMUXOUTB4→ N1W1:JDIA15_EBR_CORE
N1E1:JCIBMUXOUTA6→ N1W1:JDIA16_EBR_CORE
N1E1:JCIBMUXOUTB6→ N1W1:JDIA17_EBR_CORE
N1W1:JCIBMUXOUTB6→ N1W1:JDIA1_EBR_CORE
N1:JCIBMUXOUTB0→ N1W1:JDIA2_EBR_CORE
N1:JCIBMUXOUTA0→ N1W1:JDIA3_EBR_CORE
N1:JCIBMUXOUTB2→ N1W1:JDIA4_EBR_CORE
N1:JCIBMUXOUTA2→ N1W1:JDIA5_EBR_CORE
N1:JCIBMUXOUTA4→ N1W1:JDIA6_EBR_CORE
N1:JCIBMUXOUTC2→ N1W1:JDIA7_EBR_CORE
N1:JCIBMUXOUTA6→ N1W1:JDIA8_EBR_CORE
N1:JCIBMUXOUTD3→ N1W1:JDIA9_EBR_CORE
N1W1:JCIBMUXOUTC3→ N1W1:JDIB0_EBR_CORE
N1E1:JCIBMUXOUTC4→ N1W1:JDIB10_EBR_CORE
N1E1:JCIBMUXOUTD4→ N1W1:JDIB11_EBR_CORE
N1E1:JCIBMUXOUTD5→ N1W1:JDIB12_EBR_CORE
N1E1:JCIBMUXOUTC5→ N1W1:JDIB13_EBR_CORE
N1E1:JCIBMUXOUTD2→ N1W1:JDIB14_EBR_CORE
N1E1:JCIBMUXOUTC2→ N1W1:JDIB15_EBR_CORE
N1E1:JCIBMUXOUTC3→ N1W1:JDIB16_EBR_CORE
N1E1:JCIBMUXOUTD3→ N1W1:JDIB17_EBR_CORE
N1W1:JCIBMUXOUTD3→ N1W1:JDIB1_EBR_CORE
N1:JCIBMUXOUTC4→ N1W1:JDIB2_EBR_CORE
N1:JCIBMUXOUTD4→ N1W1:JDIB3_EBR_CORE
N1:JCIBMUXOUTD5→ N1W1:JDIB4_EBR_CORE
N1:JCIBMUXOUTC5→ N1W1:JDIB5_EBR_CORE
N1:JCIBMUXOUTD2→ N1W1:JDIB6_EBR_CORE
N1:JCIBMUXOUTB4→ N1W1:JDIB7_EBR_CORE
N1:JCIBMUXOUTC3→ N1W1:JDIB8_EBR_CORE
N1:JCIBMUXOUTB6→ N1W1:JDIB9_EBR_CORE
N1:JCIBMUXOUTA1→ N1W1:JDWS0_EBR_CORE
N1:JCIBMUXOUTA5→ N1W1:JDWS1_EBR_CORE
N1:JCIBMUXOUTC6→ N1W1:JDWS2_EBR_CORE
N1:JCIBMUXOUTB5→ N1W1:JDWS3_EBR_CORE
N1:JCIBMUXOUTC0→ N1W1:JDWS4_EBR_CORE
N1W1:JONEERR_EBR_CORE→ N1W1:JF2
N1W1:JTWOERR_EBR_CORE→ N1W1:JF3
N1W1:JDOA0_EBR_CORE→ N1W1:JF6
N1W1:JDOA1_EBR_CORE→ N1W1:JF7
N1W1:JEMPTYF_EBR_CORE→ N1W1:JQ2
N1W1:JFULLF_EBR_CORE→ N1W1:JQ3
N1W1:JAEMPTY_EBR_CORE→ N1W1:JQ4
N1W1:JAFULL_EBR_CORE→ N1W1:JQ5
N1W1:JDOB0_EBR_CORE→ N1W1:JQ6
N1W1:JDOB1_EBR_CORE→ N1W1:JQ7
N1:JLSR0→ N1W1:JRSTA_EBR_CORE
N1E1:JLSR0→ N1W1:JRSTB_EBR_CORE
N1:JLSR1→ N1W1:JWEA_EBR_CORE
N1E1:JLSR1→ N1W1:JWEB_EBR_CORE