EBR_7 Tile Documentation

Tile Bels

NameType
EBR2 OXIDE_EBR

Config Bitmap

 
 
 
 
 
 
 
 
 
 
 
 
W
F
 
F
C
A
A
W
A
A
W
O
W
 
G
W
R
C
W
W
M
C
R
C
C
 
C
 
W
 
W
 
W
 
R
 
C
 
A
 
A
 
R
O
G
C
R
F
M
F
M
F
M
F
 
 
D
 
E
M
 
E
 
E
1
E
C
E
W
E
W
E
W
E
W
E
W
E
W
F
R
F
W
F
 
 
R
F
 
F
 
F
 
F

Configuration Words

Configuration word EBR2.DP16K_MODE.CSDECODE_A

port is enabled when CS inputs match this value

EBR2.DP16K_MODE.CSDECODE_A[0]F60B0
EBR2.DP16K_MODE.CSDECODE_A[1]F62B0
EBR2.DP16K_MODE.CSDECODE_A[2]F64B0

Configuration word EBR2.DP16K_MODE.CSDECODE_B

port is enabled when CS inputs match this value

EBR2.DP16K_MODE.CSDECODE_B[0]F33B0
EBR2.DP16K_MODE.CSDECODE_B[1]F35B0
EBR2.DP16K_MODE.CSDECODE_B[2]F36B0

Configuration word EBR2.FIFO16K_MODE.ALMOST_EMPTY

FIFO 'almost empty' output threshold

EBR2.FIFO16K_MODE.ALMOST_EMPTY[0]F70B0
EBR2.FIFO16K_MODE.ALMOST_EMPTY[1]F73B0
EBR2.FIFO16K_MODE.ALMOST_EMPTY[2]F75B0
EBR2.FIFO16K_MODE.ALMOST_EMPTY[3]F77B0
EBR2.FIFO16K_MODE.ALMOST_EMPTY[4]
EBR2.FIFO16K_MODE.ALMOST_EMPTY[5]F79B0
EBR2.FIFO16K_MODE.ALMOST_EMPTY[6]
EBR2.FIFO16K_MODE.ALMOST_EMPTY[7]F81B0
EBR2.FIFO16K_MODE.ALMOST_EMPTY[8]F83B0
EBR2.FIFO16K_MODE.ALMOST_EMPTY[9]F85B0
EBR2.FIFO16K_MODE.ALMOST_EMPTY[10]F87B0
EBR2.FIFO16K_MODE.ALMOST_EMPTY[11]
EBR2.FIFO16K_MODE.ALMOST_EMPTY[12]
EBR2.FIFO16K_MODE.ALMOST_EMPTY[13]F89B0

Configuration word EBR2.FIFO16K_MODE.ALMOST_FULL

FIFO 'almost full' output threshold

EBR2.FIFO16K_MODE.ALMOST_FULL[0]
EBR2.FIFO16K_MODE.ALMOST_FULL[1]F91B0
EBR2.FIFO16K_MODE.ALMOST_FULL[2]F93B0
EBR2.FIFO16K_MODE.ALMOST_FULL[3]F95B0
EBR2.FIFO16K_MODE.ALMOST_FULL[4]F99B0
EBR2.FIFO16K_MODE.ALMOST_FULL[5]F101B0
EBR2.FIFO16K_MODE.ALMOST_FULL[6]
EBR2.FIFO16K_MODE.ALMOST_FULL[7]F103B0
EBR2.FIFO16K_MODE.ALMOST_FULL[8]F105B0
EBR2.FIFO16K_MODE.ALMOST_FULL[9]
EBR2.FIFO16K_MODE.ALMOST_FULL[10]
EBR2.FIFO16K_MODE.ALMOST_FULL[11]
EBR2.FIFO16K_MODE.ALMOST_FULL[12]
EBR2.FIFO16K_MODE.ALMOST_FULL[13]

Configuration word EBR2.FIFO16K_MODE.FULLBITS

FIFO 'full' threshold

EBR2.FIFO16K_MODE.FULLBITS[0]F59B0
EBR2.FIFO16K_MODE.FULLBITS[1]F61B0
EBR2.FIFO16K_MODE.FULLBITS[2]F63B0
EBR2.FIFO16K_MODE.FULLBITS[3]F65B0
EBR2.FIFO16K_MODE.FULLBITS[4]F13B0
EBR2.FIFO16K_MODE.FULLBITS[5]F15B0
EBR2.FIFO16K_MODE.FULLBITS[6]
EBR2.FIFO16K_MODE.FULLBITS[7]
EBR2.FIFO16K_MODE.FULLBITS[8]
EBR2.FIFO16K_MODE.FULLBITS[9]
EBR2.FIFO16K_MODE.FULLBITS[10]
EBR2.FIFO16K_MODE.FULLBITS[11]
EBR2.FIFO16K_MODE.FULLBITS[12]
EBR2.FIFO16K_MODE.FULLBITS[13]

Configuration word EBR2.PDP16K_MODE.CSDECODE_R

port is enabled when CS inputs match this value

EBR2.PDP16K_MODE.CSDECODE_R[0]F33B0
EBR2.PDP16K_MODE.CSDECODE_R[1]F35B0
EBR2.PDP16K_MODE.CSDECODE_R[2]F36B0

Configuration word EBR2.PDP16K_MODE.CSDECODE_W

port is enabled when CS inputs match this value

EBR2.PDP16K_MODE.CSDECODE_W[0]F60B0
EBR2.PDP16K_MODE.CSDECODE_W[1]F62B0
EBR2.PDP16K_MODE.CSDECODE_W[2]F64B0

Configuration word EBR2.PDPSC16K_MODE.CSDECODE_R

port is enabled when CS inputs match this value

EBR2.PDPSC16K_MODE.CSDECODE_R[0]F33B0
EBR2.PDPSC16K_MODE.CSDECODE_R[1]F35B0
EBR2.PDPSC16K_MODE.CSDECODE_R[2]F36B0

Configuration word EBR2.PDPSC16K_MODE.CSDECODE_W

port is enabled when CS inputs match this value

EBR2.PDPSC16K_MODE.CSDECODE_W[0]F60B0
EBR2.PDPSC16K_MODE.CSDECODE_W[1]F62B0
EBR2.PDPSC16K_MODE.CSDECODE_W[2]F64B0

Configuration word EBR2.SP16K_MODE.CSDECODE

port is enabled when CS inputs match this value

EBR2.SP16K_MODE.CSDECODE[0]F33B0
EBR2.SP16K_MODE.CSDECODE[1]F35B0
EBR2.SP16K_MODE.CSDECODE[2]F36B0

Configuration word EBR2.WID

unique ID for the BRAM, used to initialise it in the bitstream

EBR2.WID[0]
EBR2.WID[1]F80B0
EBR2.WID[2]
EBR2.WID[3]F82B0
EBR2.WID[4]F84B0
EBR2.WID[5]F86B0
EBR2.WID[6]F88B0
EBR2.WID[7]
EBR2.WID[8]
EBR2.WID[9]F90B0
EBR2.WID[10]

Configuration Enums

Configuration enum EBR2.DP16K_MODE.ADA0MUX

Value F18B0
ADA0 -
INV 1

Configuration enum EBR2.DP16K_MODE.ADA1MUX

Value F17B0
ADA1 -
INV 1

Configuration enum EBR2.DP16K_MODE.ADA2MUX

Value F21B0
ADA2 -
INV 1

Configuration enum EBR2.DP16K_MODE.ADA3MUX

Value F20B0
ADA3 -
INV 1

Configuration enum EBR2.DP16K_MODE.ADB0MUX

Value F50B0
ADB0 -
INV 1

Configuration enum EBR2.DP16K_MODE.ADB1MUX

Value F52B0
ADB1 -
INV 1

Configuration enum EBR2.DP16K_MODE.ASYNC_RST_RELEASE_A

Value F28B0
ASYNC 1
SYNC -

Configuration enum EBR2.DP16K_MODE.ASYNC_RST_RELEASE_B

Value F98B0
ASYNC 1
SYNC -

Configuration enum EBR2.DP16K_MODE.CEAMUX

Value F78B0
CEA -
INV 1

Configuration enum EBR2.DP16K_MODE.CEBMUX

Value F38B0
CEB -
INV 1

Configuration enum EBR2.DP16K_MODE.CLKAMUX

clock inversion control for CLKA

Value F16B0 F29B0
0 - -
CLKA 1 -
INV - 1

Configuration enum EBR2.DP16K_MODE.CLKBMUX

clock inversion control for CLKB

Value F48B0 F57B0
0 - -
CLKB - 1
INV 1 -

Configuration enum EBR2.DP16K_MODE.DATA_WIDTH_A

data width of port A in DP16K_MODE

Value F19B0 F22B0 F24B0 F27B0
X1 1 1 1 1
X18 - - - -
X2 - 1 1 1
X4 - - 1 1
X9 - - - 1

Configuration enum EBR2.DP16K_MODE.DATA_WIDTH_B

data width of port B in DP16K_MODE

Value F12B0 F40B0 F42B0 F44B0
X1 1 1 1 1
X18 - - - -
X2 1 - 1 1
X4 1 - - 1
X9 - - - 1

Configuration enum EBR2.DP16K_MODE.OUTREG_A

extra output pipeline register enable/bypass

Value F23B0
BYPASSED -
USED 1

Configuration enum EBR2.DP16K_MODE.OUTREG_B

extra output pipeline register enable/bypass

Value F55B0
BYPASSED -
USED 1

Configuration enum EBR2.DP16K_MODE.RESETMODE_A

Value F34B0
ASYNC 1
SYNC -

Configuration enum EBR2.DP16K_MODE.RESETMODE_B

Value F54B0
ASYNC 1
SYNC -

Configuration enum EBR2.DP16K_MODE.RSTAMUX

Value F92B0
INV 1
RSTA -

Configuration enum EBR2.DP16K_MODE.RSTBMUX

Value F58B0
INV 1
RSTB -

Configuration enum EBR2.DP16K_MODE.WEAMUX

Value F31B0
INV 1
WEA -

Configuration enum EBR2.DP16K_MODE.WEBMUX

Value F94B0
INV 1
WEB -

Configuration enum EBR2.FIFO16K_MODE.ASYNC_RST_RELEASE_A

Value F28B0
ASYNC 1
SYNC -

Configuration enum EBR2.FIFO16K_MODE.ASYNC_RST_RELEASE_B

Value F98B0
ASYNC 1
SYNC -

Configuration enum EBR2.FIFO16K_MODE.CEAMUX

Value F78B0
CEA -
INV 1

Configuration enum EBR2.FIFO16K_MODE.CEBMUX

Value F38B0
CEB -
INV 1

Configuration enum EBR2.FIFO16K_MODE.CKAMUX

clock inversion control for CKA

Value F16B0 F29B0
0 - -
CKA 1 -
INV - 1

Configuration enum EBR2.FIFO16K_MODE.CKBMUX

clock inversion control for CKB

Value F48B0 F57B0
0 - -
CKB - 1
INV 1 -

Configuration enum EBR2.FIFO16K_MODE.DATA_WIDTH_A

data width of port A in FIFO16K_MODE

Value F19B0 F22B0 F24B0 F27B0 F30B0
X1 1 1 1 1 1
X18 - - - - 1
X2 - 1 1 1 1
X32 - - - - -
X36 - - - - -
X4 - - 1 1 1
X9 - - - 1 1

Configuration enum EBR2.FIFO16K_MODE.DATA_WIDTH_B

data width of port B in FIFO16K_MODE

Value F12B0 F40B0 F42B0 F44B0 F46B0
X1 1 1 1 1 1
X18 - - - - 1
X2 1 - 1 1 1
X32 - - - - -
X36 - - - - -
X4 1 - - 1 1
X9 - - - 1 1

Configuration enum EBR2.FIFO16K_MODE.OUTREG_A

extra output pipeline register enable/bypass

Value F23B0
BYPASSED -
USED 1

Configuration enum EBR2.FIFO16K_MODE.OUTREG_B

extra output pipeline register enable/bypass

Value F55B0
BYPASSED -
USED 1

Configuration enum EBR2.FIFO16K_MODE.RESETMODE_A

Value F34B0
ASYNC 1
SYNC -

Configuration enum EBR2.FIFO16K_MODE.RESETMODE_B

Value F54B0
ASYNC 1
SYNC -

Configuration enum EBR2.FIFO16K_MODE.RSTAMUX

Value F92B0
INV 1
RSTA -

Configuration enum EBR2.FIFO16K_MODE.RSTBMUX

Value F58B0
INV 1
RSTB -

Configuration enum EBR2.GSR

if ENABLED, then read ports are reset by user GSR

Value F26B0 F56B0
DISABLED 1 1
ENABLED - -

Configuration enum EBR2.INIT_DATA

selects initialisation mode

Value F68B0
DYNAMIC 1
NO_INIT -
STATIC 1

Configuration enum EBR2.MODE

EBR2 primitive mode

Value F30B0 F32B0 F46B0 F60B0 F62B0 F64B0 F71B0 F94B0
DP16K_MODE 1 - 1 - - - 1 -
FIFO16K_MODE - 1 - - - - - 1
NONE - - - - - - - -
PDP16K_MODE - - - - - - 1 1
PDPSC16K_MODE - - - - - - 1 1
SP16K_MODE 1 - 1 1 1 1 1 -

Configuration enum EBR2.PDP16K_MODE.ADR0MUX

Value F50B0
ADR0 -
INV 1

Configuration enum EBR2.PDP16K_MODE.ADR1MUX

Value F52B0
ADR1 -
INV 1

Configuration enum EBR2.PDP16K_MODE.ADW0MUX

Value F18B0
ADW0 -
INV 1

Configuration enum EBR2.PDP16K_MODE.ADW1MUX

Value F17B0
ADW1 -
INV 1

Configuration enum EBR2.PDP16K_MODE.ADW2MUX

Value F21B0
ADW2 -
INV 1

Configuration enum EBR2.PDP16K_MODE.ADW3MUX

Value F20B0
ADW3 -
INV 1

Configuration enum EBR2.PDP16K_MODE.ASYNC_RST_RELEASE

Value F28B0 F98B0
ASYNC 1 1
SYNC - -

Configuration enum EBR2.PDP16K_MODE.CERMUX

Value F38B0
CER -
INV 1

Configuration enum EBR2.PDP16K_MODE.CEWMUX

Value F78B0
CEW -
INV 1

Configuration enum EBR2.PDP16K_MODE.CLKRMUX

clock inversion control for CLKR

Value F48B0 F57B0
0 - -
CLKR - 1
INV 1 -

Configuration enum EBR2.PDP16K_MODE.CLKWMUX

clock inversion control for CLKW

Value F16B0 F29B0
0 - -
CLKW 1 -
INV - 1

Configuration enum EBR2.PDP16K_MODE.DATA_WIDTH_R

data width of read port in PDP16K_MODE

Value F12B0 F40B0 F42B0 F44B0 F46B0
X1 1 1 1 1 1
X18 - - - - 1
X2 1 - 1 1 1
X32 - - - - -
X36 - - - - -
X4 1 - - 1 1
X9 - - - 1 1

Configuration enum EBR2.PDP16K_MODE.DATA_WIDTH_W

data width of write port in PDP16K_MODE

Value F19B0 F22B0 F24B0 F27B0 F30B0
X1 1 1 1 1 1
X18 - - - - 1
X2 - 1 1 1 1
X32 - - - - -
X36 - - - - -
X4 - - 1 1 1
X9 - - - 1 1

Configuration enum EBR2.PDP16K_MODE.OUTREG

extra output pipeline register enable/bypass

Value F23B0 F55B0
BYPASSED - -
USED 1 1

Configuration enum EBR2.PDP16K_MODE.RESETMODE

Value F34B0 F54B0
ASYNC 1 1
SYNC - -

Configuration enum EBR2.PDP16K_MODE.RSTMUX

Value F58B0 F92B0
INV 1 1
RST - -

Configuration enum EBR2.PDPSC16K_MODE.ADR0MUX

Value F50B0
ADR0 -
INV 1

Configuration enum EBR2.PDPSC16K_MODE.ADR1MUX

Value F52B0
ADR1 -
INV 1

Configuration enum EBR2.PDPSC16K_MODE.ADW0MUX

Value F18B0
ADW0 -
INV 1

Configuration enum EBR2.PDPSC16K_MODE.ADW1MUX

Value F17B0
ADW1 -
INV 1

Configuration enum EBR2.PDPSC16K_MODE.ADW2MUX

Value F21B0
ADW2 -
INV 1

Configuration enum EBR2.PDPSC16K_MODE.ADW3MUX

Value F20B0
ADW3 -
INV 1

Configuration enum EBR2.PDPSC16K_MODE.ASYNC_RST_RELEASE

Value F28B0 F98B0
ASYNC 1 1
SYNC - -

Configuration enum EBR2.PDPSC16K_MODE.CERMUX

Value F38B0
CER -
INV 1

Configuration enum EBR2.PDPSC16K_MODE.CEWMUX

Value F78B0
CEW -
INV 1

Configuration enum EBR2.PDPSC16K_MODE.CLKMUX

clock inversion control for CLK

Value F16B0 F29B0 F48B0 F57B0
0 - - - -
CLK 1 - - 1
INV - 1 1 -

Configuration enum EBR2.PDPSC16K_MODE.DATA_WIDTH_R

data width of read port in PDPSC16K_MODE

Value F12B0 F40B0 F42B0 F44B0 F46B0
X1 1 1 1 1 1
X18 - - - - 1
X2 1 - 1 1 1
X32 - - - - -
X36 - - - - -
X4 1 - - 1 1
X9 - - - 1 1

Configuration enum EBR2.PDPSC16K_MODE.DATA_WIDTH_W

data width of write port in PDPSC16K_MODE

Value F19B0 F22B0 F24B0 F27B0 F30B0
X1 1 1 1 1 1
X18 - - - - 1
X2 - 1 1 1 1
X32 - - - - -
X36 - - - - -
X4 - - 1 1 1
X9 - - - 1 1

Configuration enum EBR2.PDPSC16K_MODE.OUTREG

extra output pipeline register enable/bypass

Value F23B0 F55B0
BYPASSED - -
USED 1 1

Configuration enum EBR2.PDPSC16K_MODE.RESETMODE

Value F34B0 F54B0
ASYNC 1 1
SYNC - -

Configuration enum EBR2.PDPSC16K_MODE.RSTMUX

Value F58B0 F92B0
INV 1 1
RST - -

Configuration enum EBR2.SP16K_MODE.AD0MUX

Value F18B0 F50B0
AD0 - -
INV 1 1

Configuration enum EBR2.SP16K_MODE.AD1MUX

Value F17B0 F52B0
AD1 - -
INV 1 1

Configuration enum EBR2.SP16K_MODE.AD2MUX

Value F21B0
AD2 -
INV 1

Configuration enum EBR2.SP16K_MODE.AD3MUX

Value F20B0
AD3 -
INV 1

Configuration enum EBR2.SP16K_MODE.ASYNC_RST_RELEASE

Value F28B0 F98B0
ASYNC 1 1
SYNC - -

Configuration enum EBR2.SP16K_MODE.CEMUX

Value F38B0 F78B0
CE - -
INV 1 1

Configuration enum EBR2.SP16K_MODE.CLKMUX

clock inversion control for CLK

Value F16B0 F29B0 F48B0 F57B0
0 - - - -
CLK 1 - - 1
INV - 1 1 -

Configuration enum EBR2.SP16K_MODE.DATA_WIDTH

data width of R/W port in SP16K_MODE

Value F12B0 F19B0 F22B0 F24B0 F27B0 F40B0 F42B0 F44B0
X1 1 1 1 1 1 1 1 1
X18 - - - - - - - -
X2 1 - 1 1 1 - 1 1
X4 1 - - 1 1 - - 1
X9 - - - - 1 - - 1

Configuration enum EBR2.SP16K_MODE.OUTREG

extra output pipeline register enable/bypass

Value F23B0 F55B0
BYPASSED - -
USED 1 1

Configuration enum EBR2.SP16K_MODE.RESETMODE

Value F34B0 F54B0
ASYNC 1 1
SYNC - -

Configuration enum EBR2.SP16K_MODE.RSTMUX

Value F58B0 F92B0
INV 1 1
RST - -

Configuration enum EBR2.SP16K_MODE.WEMUX

Value F31B0 F94B0
INV 1 1
WE - -

Fixed Connections

SourceSink
N1W1:JDOA8_EBR_CORE→ N1:JF0
N1W1:JDOA9_EBR_CORE→ N1:JF1
N1W1:JDOA10_EBR_CORE→ N1:JF2
N1W1:JDOA11_EBR_CORE→ N1:JF3
N1W1:JDOA12_EBR_CORE→ N1:JF4
N1W1:JDOA13_EBR_CORE→ N1:JF5
N1W1:JDOA14_EBR_CORE→ N1:JF6
N1W1:JDOA15_EBR_CORE→ N1:JF7
N1W1:JDOB8_EBR_CORE→ N1:JQ0
N1W1:JDOB9_EBR_CORE→ N1:JQ1
N1W1:JDOB10_EBR_CORE→ N1:JQ2
N1W1:JDOB11_EBR_CORE→ N1:JQ3
N1W1:JDOB12_EBR_CORE→ N1:JQ4
N1W1:JDOB13_EBR_CORE→ N1:JQ5
N1W1:JDOB14_EBR_CORE→ N1:JQ6
N1W1:JDOB15_EBR_CORE→ N1:JQ7
N1W1:JDOA16_EBR_CORE→ N1E1:JF0
N1W1:JDOA17_EBR_CORE→ N1E1:JF1
N1W1:JDOB16_EBR_CORE→ N1E1:JQ0
N1W1:JDOB17_EBR_CORE→ N1E1:JQ1
N1:JCIBMUXOUTA3→ N1W1:JADA0_EBR_CORE
N1W2:JCIBMUXOUTD7→ N1W1:JADA10_EBR_CORE
N1W2:JCIBMUXOUTA4→ N1W1:JADA11_EBR_CORE
N1W1:JCIBMUXOUTC7→ N1W1:JADA12_EBR_CORE
N1W2:JCIBMUXOUTB3→ N1W1:JADA13_EBR_CORE
N1:JCIBMUXOUTA5→ N1W1:JADA1_EBR_CORE
N1E1:JCIBMUXOUTB1→ N1W1:JADA2_EBR_CORE
N1:JCIBMUXOUTB5→ N1W1:JADA3_EBR_CORE
N1W2:JCIBMUXOUTC1→ N1W1:JADA4_EBR_CORE
N1W1:JCIBMUXOUTB3→ N1W1:JADA5_EBR_CORE
N1W2:JCIBMUXOUTD6→ N1W1:JADA6_EBR_CORE
N1W2:JCIBMUXOUTB7→ N1W1:JADA7_EBR_CORE
N1W2:JCIBMUXOUTC2→ N1W1:JADA8_EBR_CORE
N1W2:JCIBMUXOUTA1→ N1W1:JADA9_EBR_CORE
N1:JCIBMUXOUTC6→ N1W1:JADB0_EBR_CORE
N1W1:JCIBMUXOUTD7→ N1W1:JADB10_EBR_CORE
N1W2:JCIBMUXOUTA6→ N1W1:JADB11_EBR_CORE
N1:JCIBMUXOUTD6→ N1W1:JADB12_EBR_CORE
N1:JCIBMUXOUTB3→ N1W1:JADB13_EBR_CORE
N1:JCIBMUXOUTC7→ N1W1:JADB1_EBR_CORE
N1E1:JCIBMUXOUTD0→ N1W1:JADB2_EBR_CORE
N1:JCIBMUXOUTD1→ N1W1:JADB3_EBR_CORE
N1W2:JCIBMUXOUTD2→ N1W1:JADB4_EBR_CORE
N1:JCIBMUXOUTB1→ N1W1:JADB5_EBR_CORE
N1W1:JCIBMUXOUTD6→ N1W1:JADB6_EBR_CORE
N1W2:JCIBMUXOUTB6→ N1W1:JADB7_EBR_CORE
N1W2:JCIBMUXOUTD3→ N1W1:JADB8_EBR_CORE
N1W1:JCIBMUXOUTA3→ N1W1:JADB9_EBR_CORE
N1W1:JCE0→ N1W1:JCEA_EBR_CORE
N1:JCE0→ N1W1:JCEB_EBR_CORE
N1E1:JCLK0→ N1W1:JCLKA_EBR_CORE
N1E1:JCLK1→ N1W1:JCLKB_EBR_CORE
N1W1:JCE1→ N1W1:JCSA0_EBR_CORE
N1W1:JCLK1→ N1W1:JCSA1_EBR_CORE
N1E1:JCE1→ N1W1:JCSA2_EBR_CORE
N1:JCE1→ N1W1:JCSB0_EBR_CORE
N1:JCLK1→ N1W1:JCSB1_EBR_CORE
N1E1:JLSR1→ N1W1:JCSB2_EBR_CORE
N1W1:JCIBMUXOUTB0→ N1W1:JDIA0_EBR_CORE
N1:JCIBMUXOUTB2→ N1W1:JDIA10_EBR_CORE
N1:JCIBMUXOUTC5→ N1W1:JDIA11_EBR_CORE
N1:JCIBMUXOUTA4→ N1W1:JDIA12_EBR_CORE
N1:JCIBMUXOUTB4→ N1W1:JDIA13_EBR_CORE
N1:JCIBMUXOUTA6→ N1W1:JDIA14_EBR_CORE
N1:JCIBMUXOUTB6→ N1W1:JDIA15_EBR_CORE
N1E1:JCIBMUXOUTB0→ N1W1:JDIA16_EBR_CORE
N1E1:JCIBMUXOUTA0→ N1W1:JDIA17_EBR_CORE
N1W1:JCIBMUXOUTA0→ N1W1:JDIA1_EBR_CORE
N1W1:JCIBMUXOUTB2→ N1W1:JDIA2_EBR_CORE
N1W1:JCIBMUXOUTA2→ N1W1:JDIA3_EBR_CORE
N1W1:JCIBMUXOUTA4→ N1W1:JDIA4_EBR_CORE
N1W1:JCIBMUXOUTB4→ N1W1:JDIA5_EBR_CORE
N1W1:JCIBMUXOUTA6→ N1W1:JDIA6_EBR_CORE
N1W1:JCIBMUXOUTB6→ N1W1:JDIA7_EBR_CORE
N1:JCIBMUXOUTB0→ N1W1:JDIA8_EBR_CORE
N1:JCIBMUXOUTD4→ N1W1:JDIA9_EBR_CORE
N1W1:JCIBMUXOUTC4→ N1W1:JDIB0_EBR_CORE
N1:JCIBMUXOUTD5→ N1W1:JDIB10_EBR_CORE
N1:JCIBMUXOUTA2→ N1W1:JDIB11_EBR_CORE
N1:JCIBMUXOUTD2→ N1W1:JDIB12_EBR_CORE
N1:JCIBMUXOUTC2→ N1W1:JDIB13_EBR_CORE
N1:JCIBMUXOUTC3→ N1W1:JDIB14_EBR_CORE
N1:JCIBMUXOUTD3→ N1W1:JDIB15_EBR_CORE
N1E1:JCIBMUXOUTC4→ N1W1:JDIB16_EBR_CORE
N1E1:JCIBMUXOUTD4→ N1W1:JDIB17_EBR_CORE
N1W1:JCIBMUXOUTD4→ N1W1:JDIB1_EBR_CORE
N1W1:JCIBMUXOUTD5→ N1W1:JDIB2_EBR_CORE
N1W1:JCIBMUXOUTC5→ N1W1:JDIB3_EBR_CORE
N1W1:JCIBMUXOUTD2→ N1W1:JDIB4_EBR_CORE
N1W1:JCIBMUXOUTC2→ N1W1:JDIB5_EBR_CORE
N1W1:JCIBMUXOUTC3→ N1W1:JDIB6_EBR_CORE
N1W1:JCIBMUXOUTD3→ N1W1:JDIB7_EBR_CORE
N1:JCIBMUXOUTC4→ N1W1:JDIB8_EBR_CORE
N1:JCIBMUXOUTA0→ N1W1:JDIB9_EBR_CORE
N1W1:JCIBMUXOUTA1→ N1W1:JDWS0_EBR_CORE
N1W1:JCIBMUXOUTA5→ N1W1:JDWS1_EBR_CORE
N1W1:JCIBMUXOUTC6→ N1W1:JDWS2_EBR_CORE
N1W1:JCIBMUXOUTB5→ N1W1:JDWS3_EBR_CORE
N1W1:JCIBMUXOUTC0→ N1W1:JDWS4_EBR_CORE
N1W1:JDOA0_EBR_CORE→ N1W1:JF0
N1W1:JDOA1_EBR_CORE→ N1W1:JF1
N1W1:JDOA2_EBR_CORE→ N1W1:JF2
N1W1:JDOA3_EBR_CORE→ N1W1:JF3
N1W1:JDOA4_EBR_CORE→ N1W1:JF4
N1W1:JDOA5_EBR_CORE→ N1W1:JF5
N1W1:JDOA6_EBR_CORE→ N1W1:JF6
N1W1:JDOA7_EBR_CORE→ N1W1:JF7
N1W1:JDOB0_EBR_CORE→ N1W1:JQ0
N1W1:JDOB1_EBR_CORE→ N1W1:JQ1
N1W1:JDOB2_EBR_CORE→ N1W1:JQ2
N1W1:JDOB3_EBR_CORE→ N1W1:JQ3
N1W1:JDOB4_EBR_CORE→ N1W1:JQ4
N1W1:JDOB5_EBR_CORE→ N1W1:JQ5
N1W1:JDOB6_EBR_CORE→ N1W1:JQ6
N1W1:JDOB7_EBR_CORE→ N1W1:JQ7
N1W1:JLSR0→ N1W1:JRSTA_EBR_CORE
N1:JLSR0→ N1W1:JRSTB_EBR_CORE
N1W1:JLSR1→ N1W1:JWEA_EBR_CORE
N1:JLSR1→ N1W1:JWEB_EBR_CORE
N1W1:JONEERR_EBR_CORE→ N1W2:JF4
N1W1:JTWOERR_EBR_CORE→ N1W2:JF5
N1W1:JEMPTYF_EBR_CORE→ N1W2:JQ4
N1W1:JFULLF_EBR_CORE→ N1W2:JQ5
N1W1:JAEMPTY_EBR_CORE→ N1W2:JQ6
N1W1:JAFULL_EBR_CORE→ N1W2:JQ7