EBR_4 Tile Documentation

Tile Bels

NameType
EBR1 OXIDE_EBR

Config Bitmap

 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
C
C
A
A
W
A
A
W
O
W
 
G
W
R
C
W
W
M
R
C
C
 
C
 
W
 
W
 
W
 
W
 
R
 
C
 
A
 
A
 
R
O
G
C
R
F
M
F
M
F
M
F
 
F
 
 
F
D
 
E
 
 
M
 
E
 
E
1
E
C

Configuration Words

Configuration word EBR1.DP16K_MODE.CSDECODE_A

port is enabled when CS inputs match this value

EBR1.DP16K_MODE.CSDECODE_A[0]F82B0
EBR1.DP16K_MODE.CSDECODE_A[1]F84B0
EBR1.DP16K_MODE.CSDECODE_A[2]F86B0

Configuration word EBR1.DP16K_MODE.CSDECODE_B

port is enabled when CS inputs match this value

EBR1.DP16K_MODE.CSDECODE_B[0]F36B0
EBR1.DP16K_MODE.CSDECODE_B[1]F55B0
EBR1.DP16K_MODE.CSDECODE_B[2]F56B0

Configuration word EBR1.FIFO16K_MODE.ALMOST_EMPTY

FIFO 'almost empty' output threshold

EBR1.FIFO16K_MODE.ALMOST_EMPTY[0]F95B0
EBR1.FIFO16K_MODE.ALMOST_EMPTY[1]F100B0
EBR1.FIFO16K_MODE.ALMOST_EMPTY[2]F102B0
EBR1.FIFO16K_MODE.ALMOST_EMPTY[3]F104B0
EBR1.FIFO16K_MODE.ALMOST_EMPTY[4]
EBR1.FIFO16K_MODE.ALMOST_EMPTY[5]
EBR1.FIFO16K_MODE.ALMOST_EMPTY[6]
EBR1.FIFO16K_MODE.ALMOST_EMPTY[7]
EBR1.FIFO16K_MODE.ALMOST_EMPTY[8]
EBR1.FIFO16K_MODE.ALMOST_EMPTY[9]
EBR1.FIFO16K_MODE.ALMOST_EMPTY[10]
EBR1.FIFO16K_MODE.ALMOST_EMPTY[11]
EBR1.FIFO16K_MODE.ALMOST_EMPTY[12]
EBR1.FIFO16K_MODE.ALMOST_EMPTY[13]

Configuration word EBR1.FIFO16K_MODE.FULLBITS

FIFO 'full' threshold

EBR1.FIFO16K_MODE.FULLBITS[0]F81B0
EBR1.FIFO16K_MODE.FULLBITS[1]F83B0
EBR1.FIFO16K_MODE.FULLBITS[2]F85B0
EBR1.FIFO16K_MODE.FULLBITS[3]F87B0
EBR1.FIFO16K_MODE.FULLBITS[4]F89B0
EBR1.FIFO16K_MODE.FULLBITS[5]F92B0
EBR1.FIFO16K_MODE.FULLBITS[6]
EBR1.FIFO16K_MODE.FULLBITS[7]
EBR1.FIFO16K_MODE.FULLBITS[8]
EBR1.FIFO16K_MODE.FULLBITS[9]
EBR1.FIFO16K_MODE.FULLBITS[10]
EBR1.FIFO16K_MODE.FULLBITS[11]
EBR1.FIFO16K_MODE.FULLBITS[12]
EBR1.FIFO16K_MODE.FULLBITS[13]

Configuration word EBR1.PDP16K_MODE.CSDECODE_R

port is enabled when CS inputs match this value

EBR1.PDP16K_MODE.CSDECODE_R[0]F36B0
EBR1.PDP16K_MODE.CSDECODE_R[1]F55B0
EBR1.PDP16K_MODE.CSDECODE_R[2]F56B0

Configuration word EBR1.PDP16K_MODE.CSDECODE_W

port is enabled when CS inputs match this value

EBR1.PDP16K_MODE.CSDECODE_W[0]F82B0
EBR1.PDP16K_MODE.CSDECODE_W[1]F84B0
EBR1.PDP16K_MODE.CSDECODE_W[2]F86B0

Configuration word EBR1.PDPSC16K_MODE.CSDECODE_R

port is enabled when CS inputs match this value

EBR1.PDPSC16K_MODE.CSDECODE_R[0]F36B0
EBR1.PDPSC16K_MODE.CSDECODE_R[1]F55B0
EBR1.PDPSC16K_MODE.CSDECODE_R[2]F56B0

Configuration word EBR1.PDPSC16K_MODE.CSDECODE_W

port is enabled when CS inputs match this value

EBR1.PDPSC16K_MODE.CSDECODE_W[0]F82B0
EBR1.PDPSC16K_MODE.CSDECODE_W[1]F84B0
EBR1.PDPSC16K_MODE.CSDECODE_W[2]F86B0

Configuration word EBR1.SP16K_MODE.CSDECODE

port is enabled when CS inputs match this value

EBR1.SP16K_MODE.CSDECODE[0]F36B0
EBR1.SP16K_MODE.CSDECODE[1]F55B0
EBR1.SP16K_MODE.CSDECODE[2]F56B0

Configuration Enums

Configuration enum EBR1.DP16K_MODE.ADA0MUX

Value F39B0
ADA0 -
INV 1

Configuration enum EBR1.DP16K_MODE.ADA1MUX

Value F38B0
ADA1 -
INV 1

Configuration enum EBR1.DP16K_MODE.ADA2MUX

Value F42B0
ADA2 -
INV 1

Configuration enum EBR1.DP16K_MODE.ADA3MUX

Value F41B0
ADA3 -
INV 1

Configuration enum EBR1.DP16K_MODE.ADB0MUX

Value F72B0
ADB0 -
INV 1

Configuration enum EBR1.DP16K_MODE.ADB1MUX

Value F74B0
ADB1 -
INV 1

Configuration enum EBR1.DP16K_MODE.ASYNC_RST_RELEASE_A

Value F49B0
ASYNC 1
SYNC -

Configuration enum EBR1.DP16K_MODE.CEAMUX

Value F105B0
CEA -
INV 1

Configuration enum EBR1.DP16K_MODE.CEBMUX

Value F58B0
CEB -
INV 1

Configuration enum EBR1.DP16K_MODE.CLKAMUX

clock inversion control for CLKA

Value F37B0 F50B0
0 - -
CLKA 1 -
INV - 1

Configuration enum EBR1.DP16K_MODE.CLKBMUX

clock inversion control for CLKB

Value F70B0 F79B0
0 - -
CLKB - 1
INV 1 -

Configuration enum EBR1.DP16K_MODE.DATA_WIDTH_A

data width of port A in DP16K_MODE

Value F40B0 F43B0 F45B0 F48B0
X1 1 1 1 1
X18 - - - -
X2 - 1 1 1
X4 - - 1 1
X9 - - - 1

Configuration enum EBR1.DP16K_MODE.DATA_WIDTH_B

data width of port B in DP16K_MODE

Value F60B0 F62B0 F64B0 F66B0
X1 1 1 1 1
X18 - - - -
X2 - 1 1 1
X4 - - 1 1
X9 - - - 1

Configuration enum EBR1.DP16K_MODE.OUTREG_A

extra output pipeline register enable/bypass

Value F44B0
BYPASSED -
USED 1

Configuration enum EBR1.DP16K_MODE.OUTREG_B

extra output pipeline register enable/bypass

Value F77B0
BYPASSED -
USED 1

Configuration enum EBR1.DP16K_MODE.RESETMODE_A

Value F54B0
ASYNC 1
SYNC -

Configuration enum EBR1.DP16K_MODE.RESETMODE_B

Value F76B0
ASYNC 1
SYNC -

Configuration enum EBR1.DP16K_MODE.RSTBMUX

Value F80B0
INV 1
RSTB -

Configuration enum EBR1.DP16K_MODE.WEAMUX

Value F52B0
INV 1
WEA -

Configuration enum EBR1.FIFO16K_MODE.ASYNC_RST_RELEASE_A

Value F49B0
ASYNC 1
SYNC -

Configuration enum EBR1.FIFO16K_MODE.CEAMUX

Value F105B0
CEA -
INV 1

Configuration enum EBR1.FIFO16K_MODE.CEBMUX

Value F58B0
CEB -
INV 1

Configuration enum EBR1.FIFO16K_MODE.CKAMUX

clock inversion control for CKA

Value F37B0 F50B0
0 - -
CKA 1 -
INV - 1

Configuration enum EBR1.FIFO16K_MODE.CKBMUX

clock inversion control for CKB

Value F70B0 F79B0
0 - -
CKB - 1
INV 1 -

Configuration enum EBR1.FIFO16K_MODE.DATA_WIDTH_A

data width of port A in FIFO16K_MODE

Value F40B0 F43B0 F45B0 F48B0 F51B0
X1 1 1 1 1 1
X18 - - - - 1
X2 - 1 1 1 1
X32 - - - - -
X36 - - - - -
X4 - - 1 1 1
X9 - - - 1 1

Configuration enum EBR1.FIFO16K_MODE.DATA_WIDTH_B

data width of port B in FIFO16K_MODE

Value F60B0 F62B0 F64B0 F66B0 F68B0
X1 1 1 1 1 1
X18 - - - - 1
X2 - 1 1 1 1
X32 - - - - -
X36 - - - - -
X4 - - 1 1 1
X9 - - - 1 1

Configuration enum EBR1.FIFO16K_MODE.OUTREG_A

extra output pipeline register enable/bypass

Value F44B0
BYPASSED -
USED 1

Configuration enum EBR1.FIFO16K_MODE.OUTREG_B

extra output pipeline register enable/bypass

Value F77B0
BYPASSED -
USED 1

Configuration enum EBR1.FIFO16K_MODE.RESETMODE_A

Value F54B0
ASYNC 1
SYNC -

Configuration enum EBR1.FIFO16K_MODE.RESETMODE_B

Value F76B0
ASYNC 1
SYNC -

Configuration enum EBR1.FIFO16K_MODE.RSTBMUX

Value F80B0
INV 1
RSTB -

Configuration enum EBR1.GSR

if ENABLED, then read ports are reset by user GSR

Value F47B0 F78B0
DISABLED 1 1
ENABLED - -

Configuration enum EBR1.INIT_DATA

selects initialisation mode

Value F93B0
DYNAMIC 1
NO_INIT -
STATIC 1

Configuration enum EBR1.MODE

EBR1 primitive mode

Value F51B0 F53B0 F68B0 F82B0 F84B0 F86B0 F98B0
DP16K_MODE 1 - 1 - - - 1
FIFO16K_MODE - 1 - - - - -
NONE - - - - - - -
PDP16K_MODE - - - - - - 1
PDPSC16K_MODE - - - - - - 1
SP16K_MODE 1 - 1 1 1 1 1

Configuration enum EBR1.PDP16K_MODE.ADR0MUX

Value F72B0
ADR0 -
INV 1

Configuration enum EBR1.PDP16K_MODE.ADR1MUX

Value F74B0
ADR1 -
INV 1

Configuration enum EBR1.PDP16K_MODE.ADW0MUX

Value F39B0
ADW0 -
INV 1

Configuration enum EBR1.PDP16K_MODE.ADW1MUX

Value F38B0
ADW1 -
INV 1

Configuration enum EBR1.PDP16K_MODE.ADW2MUX

Value F42B0
ADW2 -
INV 1

Configuration enum EBR1.PDP16K_MODE.ADW3MUX

Value F41B0
ADW3 -
INV 1

Configuration enum EBR1.PDP16K_MODE.ASYNC_RST_RELEASE

Value F49B0
ASYNC 1
SYNC -

Configuration enum EBR1.PDP16K_MODE.CERMUX

Value F58B0
CER -
INV 1

Configuration enum EBR1.PDP16K_MODE.CEWMUX

Value F105B0
CEW -
INV 1

Configuration enum EBR1.PDP16K_MODE.CLKRMUX

clock inversion control for CLKR

Value F70B0 F79B0
0 - -
CLKR - 1
INV 1 -

Configuration enum EBR1.PDP16K_MODE.CLKWMUX

clock inversion control for CLKW

Value F37B0 F50B0
0 - -
CLKW 1 -
INV - 1

Configuration enum EBR1.PDP16K_MODE.DATA_WIDTH_R

data width of read port in PDP16K_MODE

Value F60B0 F62B0 F64B0 F66B0 F68B0
X1 1 1 1 1 1
X18 - - - - 1
X2 - 1 1 1 1
X32 - - - - -
X36 - - - - -
X4 - - 1 1 1
X9 - - - 1 1

Configuration enum EBR1.PDP16K_MODE.DATA_WIDTH_W

data width of write port in PDP16K_MODE

Value F40B0 F43B0 F45B0 F48B0 F51B0
X1 1 1 1 1 1
X18 - - - - 1
X2 - 1 1 1 1
X32 - - - - -
X36 - - - - -
X4 - - 1 1 1
X9 - - - 1 1

Configuration enum EBR1.PDP16K_MODE.OUTREG

extra output pipeline register enable/bypass

Value F44B0 F77B0
BYPASSED - -
USED 1 1

Configuration enum EBR1.PDP16K_MODE.RESETMODE

Value F54B0 F76B0
ASYNC 1 1
SYNC - -

Configuration enum EBR1.PDP16K_MODE.RSTMUX

Value F80B0
INV 1
RST -

Configuration enum EBR1.PDPSC16K_MODE.ADR0MUX

Value F72B0
ADR0 -
INV 1

Configuration enum EBR1.PDPSC16K_MODE.ADR1MUX

Value F74B0
ADR1 -
INV 1

Configuration enum EBR1.PDPSC16K_MODE.ADW0MUX

Value F39B0
ADW0 -
INV 1

Configuration enum EBR1.PDPSC16K_MODE.ADW1MUX

Value F38B0
ADW1 -
INV 1

Configuration enum EBR1.PDPSC16K_MODE.ADW2MUX

Value F42B0
ADW2 -
INV 1

Configuration enum EBR1.PDPSC16K_MODE.ADW3MUX

Value F41B0
ADW3 -
INV 1

Configuration enum EBR1.PDPSC16K_MODE.ASYNC_RST_RELEASE

Value F49B0
ASYNC 1
SYNC -

Configuration enum EBR1.PDPSC16K_MODE.CERMUX

Value F58B0
CER -
INV 1

Configuration enum EBR1.PDPSC16K_MODE.CEWMUX

Value F105B0
CEW -
INV 1

Configuration enum EBR1.PDPSC16K_MODE.CLKMUX

clock inversion control for CLK

Value F37B0 F50B0 F70B0 F79B0
0 - - - -
CLK 1 - - 1
INV - 1 1 -

Configuration enum EBR1.PDPSC16K_MODE.DATA_WIDTH_R

data width of read port in PDPSC16K_MODE

Value F60B0 F62B0 F64B0 F66B0 F68B0
X1 1 1 1 1 1
X18 - - - - 1
X2 - 1 1 1 1
X32 - - - - -
X36 - - - - -
X4 - - 1 1 1
X9 - - - 1 1

Configuration enum EBR1.PDPSC16K_MODE.DATA_WIDTH_W

data width of write port in PDPSC16K_MODE

Value F40B0 F43B0 F45B0 F48B0 F51B0
X1 1 1 1 1 1
X18 - - - - 1
X2 - 1 1 1 1
X32 - - - - -
X36 - - - - -
X4 - - 1 1 1
X9 - - - 1 1

Configuration enum EBR1.PDPSC16K_MODE.OUTREG

extra output pipeline register enable/bypass

Value F44B0 F77B0
BYPASSED - -
USED 1 1

Configuration enum EBR1.PDPSC16K_MODE.RESETMODE

Value F54B0 F76B0
ASYNC 1 1
SYNC - -

Configuration enum EBR1.PDPSC16K_MODE.RSTMUX

Value F80B0
INV 1
RST -

Configuration enum EBR1.SP16K_MODE.AD0MUX

Value F39B0 F72B0
AD0 - -
INV 1 1

Configuration enum EBR1.SP16K_MODE.AD1MUX

Value F38B0 F74B0
AD1 - -
INV 1 1

Configuration enum EBR1.SP16K_MODE.AD2MUX

Value F42B0
AD2 -
INV 1

Configuration enum EBR1.SP16K_MODE.AD3MUX

Value F41B0
AD3 -
INV 1

Configuration enum EBR1.SP16K_MODE.ASYNC_RST_RELEASE

Value F49B0
ASYNC 1
SYNC -

Configuration enum EBR1.SP16K_MODE.CEMUX

Value F58B0 F105B0
CE - -
INV 1 1

Configuration enum EBR1.SP16K_MODE.CLKMUX

clock inversion control for CLK

Value F37B0 F50B0 F70B0 F79B0
0 - - - -
CLK 1 - - 1
INV - 1 1 -

Configuration enum EBR1.SP16K_MODE.DATA_WIDTH

data width of R/W port in SP16K_MODE

Value F40B0 F43B0 F45B0 F48B0 F60B0 F62B0 F64B0 F66B0
X1 1 1 1 1 1 1 1 1
X18 - - - - - - - -
X2 - 1 1 1 - 1 1 1
X4 - - 1 1 - - 1 1
X9 - - - 1 - - - 1

Configuration enum EBR1.SP16K_MODE.OUTREG

extra output pipeline register enable/bypass

Value F44B0 F77B0
BYPASSED - -
USED 1 1

Configuration enum EBR1.SP16K_MODE.RESETMODE

Value F54B0 F76B0
ASYNC 1 1
SYNC - -

Configuration enum EBR1.SP16K_MODE.RSTMUX

Value F80B0
INV 1
RST -

Configuration enum EBR1.SP16K_MODE.WEMUX

Value F52B0
INV 1
WE -

Fixed Connections

SourceSink
N1W1:JDOA6_EBR_CORE→ N1:JF0
N1W1:JDOA7_EBR_CORE→ N1:JF1
N1W1:JDOA8_EBR_CORE→ N1:JF2
N1W1:JDOA9_EBR_CORE→ N1:JF3
N1W1:JDOA10_EBR_CORE→ N1:JF4
N1W1:JDOA11_EBR_CORE→ N1:JF5
N1W1:JDOA12_EBR_CORE→ N1:JF6
N1W1:JDOA13_EBR_CORE→ N1:JF7
N1W1:JDOB6_EBR_CORE→ N1:JQ0
N1W1:JDOB7_EBR_CORE→ N1:JQ1
N1W1:JDOB8_EBR_CORE→ N1:JQ2
N1W1:JDOB9_EBR_CORE→ N1:JQ3
N1W1:JDOB10_EBR_CORE→ N1:JQ4
N1W1:JDOB11_EBR_CORE→ N1:JQ5
N1W1:JDOB12_EBR_CORE→ N1:JQ6
N1W1:JDOB13_EBR_CORE→ N1:JQ7
N1W1:JDOA14_EBR_CORE→ N1E1:JF0
N1W1:JDOA15_EBR_CORE→ N1E1:JF1
N1W1:JDOA16_EBR_CORE→ N1E1:JF2
N1W1:JDOA17_EBR_CORE→ N1E1:JF3
N1W1:JDOB14_EBR_CORE→ N1E1:JQ0
N1W1:JDOB15_EBR_CORE→ N1E1:JQ1
N1W1:JDOB16_EBR_CORE→ N1E1:JQ2
N1W1:JDOB17_EBR_CORE→ N1E1:JQ3
N1E1:JCIBMUXOUTA3→ N1W1:JADA0_EBR_CORE
N1W2:JCIBMUXOUTD7→ N1W1:JADA10_EBR_CORE
N1W2:JCIBMUXOUTA7→ N1W1:JADA11_EBR_CORE
N1W1:JCIBMUXOUTC7→ N1W1:JADA12_EBR_CORE
N1W2:JCIBMUXOUTB3→ N1W1:JADA13_EBR_CORE
N1E1:JCIBMUXOUTA5→ N1W1:JADA1_EBR_CORE
N1E1:JCIBMUXOUTB1→ N1W1:JADA2_EBR_CORE
N1E1:JCIBMUXOUTB5→ N1W1:JADA3_EBR_CORE
N1W1:JCIBMUXOUTD0→ N1W1:JADA4_EBR_CORE
N1W1:JCIBMUXOUTB1→ N1W1:JADA5_EBR_CORE
N1W2:JCIBMUXOUTD6→ N1W1:JADA6_EBR_CORE
N1W2:JCIBMUXOUTB7→ N1W1:JADA7_EBR_CORE
N1W1:JCIBMUXOUTD1→ N1W1:JADA8_EBR_CORE
N1W2:JCIBMUXOUTA1→ N1W1:JADA9_EBR_CORE
N1E1:JCIBMUXOUTC6→ N1W1:JADB0_EBR_CORE
N1W1:JCIBMUXOUTD7→ N1W1:JADB10_EBR_CORE
N1W1:JCIBMUXOUTA5→ N1W1:JADB11_EBR_CORE
N1:JCIBMUXOUTC7→ N1W1:JADB12_EBR_CORE
N1W1:JCIBMUXOUTB3→ N1W1:JADB13_EBR_CORE
N1E1:JCIBMUXOUTC7→ N1W1:JADB1_EBR_CORE
N1E1:JCIBMUXOUTD0→ N1W1:JADB2_EBR_CORE
N1E1:JCIBMUXOUTD1→ N1W1:JADB3_EBR_CORE
N1:JCIBMUXOUTD0→ N1W1:JADB4_EBR_CORE
N1:JCIBMUXOUTB1→ N1W1:JADB5_EBR_CORE
N1W1:JCIBMUXOUTD6→ N1W1:JADB6_EBR_CORE
N1W1:JCIBMUXOUTB5→ N1W1:JADB7_EBR_CORE
N1:JCIBMUXOUTD1→ N1W1:JADB8_EBR_CORE
N1W1:JCIBMUXOUTA1→ N1W1:JADB9_EBR_CORE
N1W1:JCE0→ N1W1:JCEA_EBR_CORE
N1:JCE0→ N1W1:JCEB_EBR_CORE
N1E1:JCLK0→ N1W1:JCLKA_EBR_CORE
N1E1:JCLK1→ N1W1:JCLKB_EBR_CORE
N1W1:JCE1→ N1W1:JCSA0_EBR_CORE
N1W1:JCLK1→ N1W1:JCSA1_EBR_CORE
N1E1:JCE1→ N1W1:JCSA2_EBR_CORE
N1:JCE1→ N1W1:JCSB0_EBR_CORE
N1:JCLK1→ N1W1:JCSB1_EBR_CORE
N1E1:JLSR1→ N1W1:JCSB2_EBR_CORE
N1W1:JCIBMUXOUTB2→ N1W1:JDIA0_EBR_CORE
N1:JCIBMUXOUTA4→ N1W1:JDIA10_EBR_CORE
N1:JCIBMUXOUTC2→ N1W1:JDIA11_EBR_CORE
N1:JCIBMUXOUTA6→ N1W1:JDIA12_EBR_CORE
N1:JCIBMUXOUTB6→ N1W1:JDIA13_EBR_CORE
N1E1:JCIBMUXOUTB0→ N1W1:JDIA14_EBR_CORE
N1E1:JCIBMUXOUTA0→ N1W1:JDIA15_EBR_CORE
N1E1:JCIBMUXOUTB2→ N1W1:JDIA16_EBR_CORE
N1E1:JCIBMUXOUTA2→ N1W1:JDIA17_EBR_CORE
N1W1:JCIBMUXOUTA2→ N1W1:JDIA1_EBR_CORE
N1W1:JCIBMUXOUTA4→ N1W1:JDIA2_EBR_CORE
N1W1:JCIBMUXOUTB4→ N1W1:JDIA3_EBR_CORE
N1W1:JCIBMUXOUTA6→ N1W1:JDIA4_EBR_CORE
N1W1:JCIBMUXOUTB6→ N1W1:JDIA5_EBR_CORE
N1:JCIBMUXOUTB0→ N1W1:JDIA6_EBR_CORE
N1:JCIBMUXOUTD4→ N1W1:JDIA7_EBR_CORE
N1:JCIBMUXOUTB2→ N1W1:JDIA8_EBR_CORE
N1:JCIBMUXOUTC5→ N1W1:JDIA9_EBR_CORE
N1W1:JCIBMUXOUTD5→ N1W1:JDIB0_EBR_CORE
N1:JCIBMUXOUTD2→ N1W1:JDIB10_EBR_CORE
N1:JCIBMUXOUTB4→ N1W1:JDIB11_EBR_CORE
N1:JCIBMUXOUTC3→ N1W1:JDIB12_EBR_CORE
N1:JCIBMUXOUTD3→ N1W1:JDIB13_EBR_CORE
N1E1:JCIBMUXOUTC4→ N1W1:JDIB14_EBR_CORE
N1E1:JCIBMUXOUTD4→ N1W1:JDIB15_EBR_CORE
N1E1:JCIBMUXOUTD5→ N1W1:JDIB16_EBR_CORE
N1E1:JCIBMUXOUTC5→ N1W1:JDIB17_EBR_CORE
N1W1:JCIBMUXOUTC5→ N1W1:JDIB1_EBR_CORE
N1W1:JCIBMUXOUTD2→ N1W1:JDIB2_EBR_CORE
N1W1:JCIBMUXOUTC2→ N1W1:JDIB3_EBR_CORE
N1W1:JCIBMUXOUTC3→ N1W1:JDIB4_EBR_CORE
N1W1:JCIBMUXOUTD3→ N1W1:JDIB5_EBR_CORE
N1:JCIBMUXOUTC4→ N1W1:JDIB6_EBR_CORE
N1:JCIBMUXOUTA0→ N1W1:JDIB7_EBR_CORE
N1:JCIBMUXOUTD5→ N1W1:JDIB8_EBR_CORE
N1:JCIBMUXOUTA2→ N1W1:JDIB9_EBR_CORE
N1:JCIBMUXOUTA1→ N1W1:JDWS0_EBR_CORE
N1:JCIBMUXOUTA5→ N1W1:JDWS1_EBR_CORE
N1:JCIBMUXOUTC6→ N1W1:JDWS2_EBR_CORE
N1:JCIBMUXOUTB5→ N1W1:JDWS3_EBR_CORE
N1:JCIBMUXOUTC0→ N1W1:JDWS4_EBR_CORE
N1W1:JDOA0_EBR_CORE→ N1W1:JF2
N1W1:JDOA1_EBR_CORE→ N1W1:JF3
N1W1:JDOA2_EBR_CORE→ N1W1:JF4
N1W1:JDOA3_EBR_CORE→ N1W1:JF5
N1W1:JDOA4_EBR_CORE→ N1W1:JF6
N1W1:JDOA5_EBR_CORE→ N1W1:JF7
N1W1:JAEMPTY_EBR_CORE→ N1W1:JQ0
N1W1:JAFULL_EBR_CORE→ N1W1:JQ1
N1W1:JDOB0_EBR_CORE→ N1W1:JQ2
N1W1:JDOB1_EBR_CORE→ N1W1:JQ3
N1W1:JDOB2_EBR_CORE→ N1W1:JQ4
N1W1:JDOB3_EBR_CORE→ N1W1:JQ5
N1W1:JDOB4_EBR_CORE→ N1W1:JQ6
N1W1:JDOB5_EBR_CORE→ N1W1:JQ7
N1W1:JLSR0→ N1W1:JRSTA_EBR_CORE
N1:JLSR0→ N1W1:JRSTB_EBR_CORE
N1W1:JLSR1→ N1W1:JWEA_EBR_CORE
N1:JLSR1→ N1W1:JWEB_EBR_CORE
N1W1:JONEERR_EBR_CORE→ N1W2:JF6
N1W1:JTWOERR_EBR_CORE→ N1W2:JF7
N1W1:JEMPTYF_EBR_CORE→ N1W2:JQ6
N1W1:JFULLF_EBR_CORE→ N1W2:JQ7