EBR_2 Tile Documentation

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Configuration Words

Configuration word EBR0.DP16K_MODE.CSDECODE_A

port is enabled when CS inputs match this value

EBR0.DP16K_MODE.CSDECODE_A[0]F23B0
EBR0.DP16K_MODE.CSDECODE_A[1]F25B0
EBR0.DP16K_MODE.CSDECODE_A[2]F27B0

Configuration word EBR0.FIFO16K_MODE.ALMOST_EMPTY

FIFO 'almost empty' output threshold

EBR0.FIFO16K_MODE.ALMOST_EMPTY[0]F36B0
EBR0.FIFO16K_MODE.ALMOST_EMPTY[1]F39B0
EBR0.FIFO16K_MODE.ALMOST_EMPTY[2]F41B0
EBR0.FIFO16K_MODE.ALMOST_EMPTY[3]F43B0
EBR0.FIFO16K_MODE.ALMOST_EMPTY[4]F45B0
EBR0.FIFO16K_MODE.ALMOST_EMPTY[5]F47B0
EBR0.FIFO16K_MODE.ALMOST_EMPTY[6]F49B0
EBR0.FIFO16K_MODE.ALMOST_EMPTY[7]F51B0
EBR0.FIFO16K_MODE.ALMOST_EMPTY[8]F53B0
EBR0.FIFO16K_MODE.ALMOST_EMPTY[9]F55B0
EBR0.FIFO16K_MODE.ALMOST_EMPTY[10]F57B0
EBR0.FIFO16K_MODE.ALMOST_EMPTY[11]F59B0
EBR0.FIFO16K_MODE.ALMOST_EMPTY[12]F61B0
EBR0.FIFO16K_MODE.ALMOST_EMPTY[13]F63B0

Configuration word EBR0.FIFO16K_MODE.ALMOST_FULL

FIFO 'almost full' output threshold

EBR0.FIFO16K_MODE.ALMOST_FULL[0]F65B0
EBR0.FIFO16K_MODE.ALMOST_FULL[1]F67B0
EBR0.FIFO16K_MODE.ALMOST_FULL[2]F69B0
EBR0.FIFO16K_MODE.ALMOST_FULL[3]F71B0
EBR0.FIFO16K_MODE.ALMOST_FULL[4]F73B0
EBR0.FIFO16K_MODE.ALMOST_FULL[5]F75B0
EBR0.FIFO16K_MODE.ALMOST_FULL[6]F77B0
EBR0.FIFO16K_MODE.ALMOST_FULL[7]F79B0
EBR0.FIFO16K_MODE.ALMOST_FULL[8]F81B0
EBR0.FIFO16K_MODE.ALMOST_FULL[9]F83B0
EBR0.FIFO16K_MODE.ALMOST_FULL[10]F85B0
EBR0.FIFO16K_MODE.ALMOST_FULL[11]F87B0
EBR0.FIFO16K_MODE.ALMOST_FULL[12]F89B0
EBR0.FIFO16K_MODE.ALMOST_FULL[13]F91B0

Configuration word EBR0.FIFO16K_MODE.EMPTYBITS

FIFO 'empty' threshold

EBR0.FIFO16K_MODE.EMPTYBITS[0]F86B0
EBR0.FIFO16K_MODE.EMPTYBITS[1]F88B0
EBR0.FIFO16K_MODE.EMPTYBITS[2]F90B0
EBR0.FIFO16K_MODE.EMPTYBITS[3]F92B0
EBR0.FIFO16K_MODE.EMPTYBITS[4]F94B0

Configuration word EBR0.FIFO16K_MODE.FULLBITS

FIFO 'full' threshold

EBR0.FIFO16K_MODE.FULLBITS[0]F22B0
EBR0.FIFO16K_MODE.FULLBITS[1]F24B0
EBR0.FIFO16K_MODE.FULLBITS[2]F26B0
EBR0.FIFO16K_MODE.FULLBITS[3]F28B0
EBR0.FIFO16K_MODE.FULLBITS[4]F30B0
EBR0.FIFO16K_MODE.FULLBITS[5]F33B0
EBR0.FIFO16K_MODE.FULLBITS[6]F93B0
EBR0.FIFO16K_MODE.FULLBITS[7]F95B0
EBR0.FIFO16K_MODE.FULLBITS[8]F99B0
EBR0.FIFO16K_MODE.FULLBITS[9]F100B0
EBR0.FIFO16K_MODE.FULLBITS[10]F101B0
EBR0.FIFO16K_MODE.FULLBITS[11]F102B0
EBR0.FIFO16K_MODE.FULLBITS[12]F103B0
EBR0.FIFO16K_MODE.FULLBITS[13]F104B0

Configuration word EBR0.PDP16K_MODE.CSDECODE_W

port is enabled when CS inputs match this value

EBR0.PDP16K_MODE.CSDECODE_W[0]F23B0
EBR0.PDP16K_MODE.CSDECODE_W[1]F25B0
EBR0.PDP16K_MODE.CSDECODE_W[2]F27B0

Configuration word EBR0.PDPSC16K_MODE.CSDECODE_W

port is enabled when CS inputs match this value

EBR0.PDPSC16K_MODE.CSDECODE_W[0]F23B0
EBR0.PDPSC16K_MODE.CSDECODE_W[1]F25B0
EBR0.PDPSC16K_MODE.CSDECODE_W[2]F27B0

Configuration word EBR0.WID

unique ID for the BRAM, used to initialise it in the bitstream

EBR0.WID[0]F46B0
EBR0.WID[1]F48B0
EBR0.WID[2]F50B0
EBR0.WID[3]F52B0
EBR0.WID[4]F54B0
EBR0.WID[5]F56B0
EBR0.WID[6]F58B0
EBR0.WID[7]F60B0
EBR0.WID[8]F62B0
EBR0.WID[9]F64B0
EBR0.WID[10]F66B0

Configuration Enums

Configuration enum EBR0.DP16K_MODE.ADB0MUX

Value F13B0
ADB0 -
INV 1

Configuration enum EBR0.DP16K_MODE.ADB1MUX

Value F15B0
ADB1 -
INV 1

Configuration enum EBR0.DP16K_MODE.ASYNC_RST_RELEASE_B

Value F72B0
ASYNC 1
SYNC -

Configuration enum EBR0.DP16K_MODE.CEAMUX

Value F44B0
CEA -
INV 1

Configuration enum EBR0.DP16K_MODE.CLKBMUX

clock inversion control for CLKB

Value F11B0 F20B0
0 - -
CLKB - 1
INV 1 -

Configuration enum EBR0.DP16K_MODE.DATA_WIDTH_B

data width of port B in DP16K_MODE

Value F1B0 F3B0 F5B0 F7B0
X1 1 1 1 1
X18 - - - -
X2 - 1 1 1
X4 - - 1 1
X9 - - - 1

Configuration enum EBR0.DP16K_MODE.OUTREG_B

extra output pipeline register enable/bypass

Value F18B0
BYPASSED -
USED 1

Configuration enum EBR0.DP16K_MODE.RESETMODE_B

Value F17B0
ASYNC 1
SYNC -

Configuration enum EBR0.DP16K_MODE.RSTAMUX

Value F68B0
INV 1
RSTA -

Configuration enum EBR0.DP16K_MODE.RSTBMUX

Value F21B0
INV 1
RSTB -

Configuration enum EBR0.DP16K_MODE.WEBMUX

Value F70B0
INV 1
WEB -

Configuration enum EBR0.FIFO16K_MODE.ASYNC_RST_RELEASE_B

Value F72B0
ASYNC 1
SYNC -

Configuration enum EBR0.FIFO16K_MODE.CEAMUX

Value F44B0
CEA -
INV 1

Configuration enum EBR0.FIFO16K_MODE.CKBMUX

clock inversion control for CKB

Value F11B0 F20B0
0 - -
CKB - 1
INV 1 -

Configuration enum EBR0.FIFO16K_MODE.DATA_WIDTH_B

data width of port B in FIFO16K_MODE

Value F1B0 F3B0 F5B0 F7B0 F9B0
X1 1 1 1 1 1
X18 - - - - 1
X2 - 1 1 1 1
X32 - - - - -
X36 - - - - -
X4 - - 1 1 1
X9 - - - 1 1

Configuration enum EBR0.FIFO16K_MODE.OUTREG_B

extra output pipeline register enable/bypass

Value F18B0
BYPASSED -
USED 1

Configuration enum EBR0.FIFO16K_MODE.RESETMODE_B

Value F17B0
ASYNC 1
SYNC -

Configuration enum EBR0.FIFO16K_MODE.RSTAMUX

Value F68B0
INV 1
RSTA -

Configuration enum EBR0.FIFO16K_MODE.RSTBMUX

Value F21B0
INV 1
RSTB -

Configuration enum EBR0.GSR

if ENABLED, then read ports are reset by user GSR

Value F19B0
DISABLED 1
ENABLED -

Configuration enum EBR0.INIT_DATA

selects initialisation mode

Value F34B0
DYNAMIC 1
NO_INIT -
STATIC 1

Configuration enum EBR0.MODE

EBR0 primitive mode

Value F9B0 F23B0 F25B0 F27B0 F37B0 F70B0 F84B0 F98B0
DP16K_MODE 1 - - - 1 - - 1
FIFO16K_MODE - - - - - 1 - 1
NONE - - - - - - - -
PDP16K_MODE - - - - 1 1 - 1
PDPSC16K_MODE - - - - 1 1 1 1
SP16K_MODE 1 1 1 1 1 - 1 1

Configuration enum EBR0.PDP16K_MODE.ADR0MUX

Value F13B0
ADR0 -
INV 1

Configuration enum EBR0.PDP16K_MODE.ADR1MUX

Value F15B0
ADR1 -
INV 1

Configuration enum EBR0.PDP16K_MODE.ASYNC_RST_RELEASE

Value F72B0
ASYNC 1
SYNC -

Configuration enum EBR0.PDP16K_MODE.CEWMUX

Value F44B0
CEW -
INV 1

Configuration enum EBR0.PDP16K_MODE.CLKRMUX

clock inversion control for CLKR

Value F11B0 F20B0
0 - -
CLKR - 1
INV 1 -

Configuration enum EBR0.PDP16K_MODE.DATA_WIDTH_R

data width of read port in PDP16K_MODE

Value F1B0 F3B0 F5B0 F7B0 F9B0
X1 1 1 1 1 1
X18 - - - - 1
X2 - 1 1 1 1
X32 - - - - -
X36 - - - - -
X4 - - 1 1 1
X9 - - - 1 1

Configuration enum EBR0.PDP16K_MODE.OUTREG

extra output pipeline register enable/bypass

Value F18B0
BYPASSED -
USED 1

Configuration enum EBR0.PDP16K_MODE.RESETMODE

Value F17B0
ASYNC 1
SYNC -

Configuration enum EBR0.PDP16K_MODE.RSTMUX

Value F21B0 F68B0
INV 1 1
RST - -

Configuration enum EBR0.PDPSC16K_MODE.ADR0MUX

Value F13B0
ADR0 -
INV 1

Configuration enum EBR0.PDPSC16K_MODE.ADR1MUX

Value F15B0
ADR1 -
INV 1

Configuration enum EBR0.PDPSC16K_MODE.ASYNC_RST_RELEASE

Value F72B0
ASYNC 1
SYNC -

Configuration enum EBR0.PDPSC16K_MODE.CEWMUX

Value F44B0
CEW -
INV 1

Configuration enum EBR0.PDPSC16K_MODE.CLKMUX

clock inversion control for CLK

Value F11B0 F20B0
0 - -
CLK - 1
INV 1 -

Configuration enum EBR0.PDPSC16K_MODE.DATA_WIDTH_R

data width of read port in PDPSC16K_MODE

Value F1B0 F3B0 F5B0 F7B0 F9B0
X1 1 1 1 1 1
X18 - - - - 1
X2 - 1 1 1 1
X32 - - - - -
X36 - - - - -
X4 - - 1 1 1
X9 - - - 1 1

Configuration enum EBR0.PDPSC16K_MODE.OUTREG

extra output pipeline register enable/bypass

Value F18B0
BYPASSED -
USED 1

Configuration enum EBR0.PDPSC16K_MODE.RESETMODE

Value F17B0
ASYNC 1
SYNC -

Configuration enum EBR0.PDPSC16K_MODE.RSTMUX

Value F21B0 F68B0
INV 1 1
RST - -

Configuration enum EBR0.SP16K_MODE.AD0MUX

Value F13B0
AD0 -
INV 1

Configuration enum EBR0.SP16K_MODE.AD1MUX

Value F15B0
AD1 -
INV 1

Configuration enum EBR0.SP16K_MODE.ASYNC_RST_RELEASE

Value F72B0
ASYNC 1
SYNC -

Configuration enum EBR0.SP16K_MODE.CEMUX

Value F44B0
CE -
INV 1

Configuration enum EBR0.SP16K_MODE.CLKMUX

clock inversion control for CLK

Value F11B0 F20B0
0 - -
CLK - 1
INV 1 -

Configuration enum EBR0.SP16K_MODE.DATA_WIDTH

data width of R/W port in SP16K_MODE

Value F1B0 F3B0 F5B0 F7B0
X1 1 1 1 1
X18 - - - -
X2 - 1 1 1
X4 - - 1 1
X9 - - - 1

Configuration enum EBR0.SP16K_MODE.OUTREG

extra output pipeline register enable/bypass

Value F18B0
BYPASSED -
USED 1

Configuration enum EBR0.SP16K_MODE.RESETMODE

Value F17B0
ASYNC 1
SYNC -

Configuration enum EBR0.SP16K_MODE.RSTMUX

Value F21B0 F68B0
INV 1 1
RST - -

Configuration enum EBR0.SP16K_MODE.WEMUX

Value F70B0
INV 1
WE -