EBR_10 Tile Documentation

Config Bitmap

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Configuration Words

Configuration word EBR3.DP16K_MODE.CSDECODE_A

port is enabled when CS inputs match this value

EBR3.DP16K_MODE.CSDECODE_A[0]F47B0
EBR3.DP16K_MODE.CSDECODE_A[1]F49B0
EBR3.DP16K_MODE.CSDECODE_A[2]F51B0

Configuration word EBR3.DP16K_MODE.CSDECODE_B

port is enabled when CS inputs match this value

EBR3.DP16K_MODE.CSDECODE_B[0]F23B0
EBR3.DP16K_MODE.CSDECODE_B[1]
EBR3.DP16K_MODE.CSDECODE_B[2]

Configuration word EBR3.FIFO16K_MODE.ALMOST_EMPTY

FIFO 'almost empty' output threshold

EBR3.FIFO16K_MODE.ALMOST_EMPTY[0]F57B0
EBR3.FIFO16K_MODE.ALMOST_EMPTY[1]F60B0
EBR3.FIFO16K_MODE.ALMOST_EMPTY[2]F62B0
EBR3.FIFO16K_MODE.ALMOST_EMPTY[3]
EBR3.FIFO16K_MODE.ALMOST_EMPTY[4]
EBR3.FIFO16K_MODE.ALMOST_EMPTY[5]
EBR3.FIFO16K_MODE.ALMOST_EMPTY[6]
EBR3.FIFO16K_MODE.ALMOST_EMPTY[7]
EBR3.FIFO16K_MODE.ALMOST_EMPTY[8]
EBR3.FIFO16K_MODE.ALMOST_EMPTY[9]
EBR3.FIFO16K_MODE.ALMOST_EMPTY[10]
EBR3.FIFO16K_MODE.ALMOST_EMPTY[11]
EBR3.FIFO16K_MODE.ALMOST_EMPTY[12]
EBR3.FIFO16K_MODE.ALMOST_EMPTY[13]

Configuration word EBR3.FIFO16K_MODE.FULLBITS

FIFO 'full' threshold

EBR3.FIFO16K_MODE.FULLBITS[0]F46B0
EBR3.FIFO16K_MODE.FULLBITS[1]F48B0
EBR3.FIFO16K_MODE.FULLBITS[2]F50B0
EBR3.FIFO16K_MODE.FULLBITS[3]F52B0
EBR3.FIFO16K_MODE.FULLBITS[4]
EBR3.FIFO16K_MODE.FULLBITS[5]F54B0
EBR3.FIFO16K_MODE.FULLBITS[6]
EBR3.FIFO16K_MODE.FULLBITS[7]F0B0
EBR3.FIFO16K_MODE.FULLBITS[8]F2B0
EBR3.FIFO16K_MODE.FULLBITS[9]F3B0
EBR3.FIFO16K_MODE.FULLBITS[10]F4B0
EBR3.FIFO16K_MODE.FULLBITS[11]F5B0
EBR3.FIFO16K_MODE.FULLBITS[12]F6B0
EBR3.FIFO16K_MODE.FULLBITS[13]F7B0

Configuration word EBR3.PDP16K_MODE.CSDECODE_R

port is enabled when CS inputs match this value

EBR3.PDP16K_MODE.CSDECODE_R[0]F23B0
EBR3.PDP16K_MODE.CSDECODE_R[1]
EBR3.PDP16K_MODE.CSDECODE_R[2]

Configuration word EBR3.PDP16K_MODE.CSDECODE_W

port is enabled when CS inputs match this value

EBR3.PDP16K_MODE.CSDECODE_W[0]F47B0
EBR3.PDP16K_MODE.CSDECODE_W[1]F49B0
EBR3.PDP16K_MODE.CSDECODE_W[2]F51B0

Configuration word EBR3.PDPSC16K_MODE.CSDECODE_R

port is enabled when CS inputs match this value

EBR3.PDPSC16K_MODE.CSDECODE_R[0]F23B0
EBR3.PDPSC16K_MODE.CSDECODE_R[1]
EBR3.PDPSC16K_MODE.CSDECODE_R[2]

Configuration word EBR3.PDPSC16K_MODE.CSDECODE_W

port is enabled when CS inputs match this value

EBR3.PDPSC16K_MODE.CSDECODE_W[0]F47B0
EBR3.PDPSC16K_MODE.CSDECODE_W[1]F49B0
EBR3.PDPSC16K_MODE.CSDECODE_W[2]F51B0

Configuration word EBR3.SP16K_MODE.CSDECODE

port is enabled when CS inputs match this value

EBR3.SP16K_MODE.CSDECODE[0]F23B0
EBR3.SP16K_MODE.CSDECODE[1]
EBR3.SP16K_MODE.CSDECODE[2]

Configuration Enums

Configuration enum EBR3.DP16K_MODE.ADA0MUX

Value F10B0
ADA0 -
INV 1

Configuration enum EBR3.DP16K_MODE.ADA1MUX

Value F9B0
ADA1 -
INV 1

Configuration enum EBR3.DP16K_MODE.ADA2MUX

Value F13B0
ADA2 -
INV 1

Configuration enum EBR3.DP16K_MODE.ADA3MUX

Value F12B0
ADA3 -
INV 1

Configuration enum EBR3.DP16K_MODE.ADB0MUX

Value F37B0
ADB0 -
INV 1

Configuration enum EBR3.DP16K_MODE.ADB1MUX

Value F39B0
ADB1 -
INV 1

Configuration enum EBR3.DP16K_MODE.CLKAMUX

clock inversion control for CLKA

Value F8B0 F20B0
0 - -
CLKA 1 -
INV - 1

Configuration enum EBR3.DP16K_MODE.CLKBMUX

clock inversion control for CLKB

Value F35B0 F44B0
0 - -
CLKB - 1
INV 1 -

Configuration enum EBR3.DP16K_MODE.DATA_WIDTH_A

data width of port A in DP16K_MODE

Value F11B0 F14B0 F16B0 F19B0
X1 1 1 1 1
X18 - - - -
X2 - 1 1 1
X4 - - 1 1
X9 - - - 1

Configuration enum EBR3.DP16K_MODE.DATA_WIDTH_B

data width of port B in DP16K_MODE

Value F27B0 F29B0 F31B0
X1 1 1 1
X18 - - -
X2 - 1 1
X4 - - 1
X9 - - 1

Configuration enum EBR3.DP16K_MODE.OUTREG_A

extra output pipeline register enable/bypass

Value F15B0
BYPASSED -
USED 1

Configuration enum EBR3.DP16K_MODE.OUTREG_B

extra output pipeline register enable/bypass

Value F42B0
BYPASSED -
USED 1

Configuration enum EBR3.DP16K_MODE.RESETMODE_A

Value F24B0
ASYNC 1
SYNC -

Configuration enum EBR3.DP16K_MODE.RESETMODE_B

Value F41B0
ASYNC 1
SYNC -

Configuration enum EBR3.DP16K_MODE.RSTBMUX

Value F45B0
INV 1
RSTB -

Configuration enum EBR3.DP16K_MODE.WEAMUX

Value F21B0
INV 1
WEA -

Configuration enum EBR3.FIFO16K_MODE.CKAMUX

clock inversion control for CKA

Value F8B0 F20B0
0 - -
CKA 1 -
INV - 1

Configuration enum EBR3.FIFO16K_MODE.CKBMUX

clock inversion control for CKB

Value F35B0 F44B0
0 - -
CKB - 1
INV 1 -

Configuration enum EBR3.FIFO16K_MODE.DATA_WIDTH_A

data width of port A in FIFO16K_MODE

Value F11B0 F14B0 F16B0 F19B0
X1 1 1 1 1
X18 - - - -
X2 - 1 1 1
X32 - - - -
X36 - - - -
X4 - - 1 1
X9 - - - 1

Configuration enum EBR3.FIFO16K_MODE.DATA_WIDTH_B

data width of port B in FIFO16K_MODE

Value F27B0 F29B0 F31B0 F33B0
X1 1 1 1 1
X18 - - - 1
X2 - 1 1 1
X32 - - - -
X36 - - - -
X4 - - 1 1
X9 - - 1 1

Configuration enum EBR3.FIFO16K_MODE.OUTREG_A

extra output pipeline register enable/bypass

Value F15B0
BYPASSED -
USED 1

Configuration enum EBR3.FIFO16K_MODE.OUTREG_B

extra output pipeline register enable/bypass

Value F42B0
BYPASSED -
USED 1

Configuration enum EBR3.FIFO16K_MODE.RESETMODE_A

Value F24B0
ASYNC 1
SYNC -

Configuration enum EBR3.FIFO16K_MODE.RESETMODE_B

Value F41B0
ASYNC 1
SYNC -

Configuration enum EBR3.FIFO16K_MODE.RSTBMUX

Value F45B0
INV 1
RSTB -

Configuration enum EBR3.GSR

if ENABLED, then read ports are reset by user GSR

Value F18B0 F43B0
DISABLED 1 1
ENABLED - -

Configuration enum EBR3.INIT_DATA

selects initialisation mode

Value F55B0
DYNAMIC 1
NO_INIT -
STATIC 1

Configuration enum EBR3.MODE

EBR3 primitive mode

Value F1B0 F22B0 F33B0 F47B0 F49B0 F51B0 F58B0
DP16K_MODE 1 - 1 - - - 1
FIFO16K_MODE 1 1 - - - - -
NONE - - - - - - -
PDP16K_MODE 1 - - - - - 1
PDPSC16K_MODE 1 - - - - - 1
SP16K_MODE 1 - 1 1 1 1 1

Configuration enum EBR3.PDP16K_MODE.ADR0MUX

Value F37B0
ADR0 -
INV 1

Configuration enum EBR3.PDP16K_MODE.ADR1MUX

Value F39B0
ADR1 -
INV 1

Configuration enum EBR3.PDP16K_MODE.ADW0MUX

Value F10B0
ADW0 -
INV 1

Configuration enum EBR3.PDP16K_MODE.ADW1MUX

Value F9B0
ADW1 -
INV 1

Configuration enum EBR3.PDP16K_MODE.ADW2MUX

Value F13B0
ADW2 -
INV 1

Configuration enum EBR3.PDP16K_MODE.ADW3MUX

Value F12B0
ADW3 -
INV 1

Configuration enum EBR3.PDP16K_MODE.CLKRMUX

clock inversion control for CLKR

Value F35B0 F44B0
0 - -
CLKR - 1
INV 1 -

Configuration enum EBR3.PDP16K_MODE.CLKWMUX

clock inversion control for CLKW

Value F8B0 F20B0
0 - -
CLKW 1 -
INV - 1

Configuration enum EBR3.PDP16K_MODE.DATA_WIDTH_R

data width of read port in PDP16K_MODE

Value F27B0 F29B0 F31B0 F33B0
X1 1 1 1 1
X18 - - - 1
X2 - 1 1 1
X32 - - - -
X36 - - - -
X4 - - 1 1
X9 - - 1 1

Configuration enum EBR3.PDP16K_MODE.DATA_WIDTH_W

data width of write port in PDP16K_MODE

Value F11B0 F14B0 F16B0 F19B0
X1 1 1 1 1
X18 - - - -
X2 - 1 1 1
X32 - - - -
X36 - - - -
X4 - - 1 1
X9 - - - 1

Configuration enum EBR3.PDP16K_MODE.OUTREG

extra output pipeline register enable/bypass

Value F15B0 F42B0
BYPASSED - -
USED 1 1

Configuration enum EBR3.PDP16K_MODE.RESETMODE

Value F24B0 F41B0
ASYNC 1 1
SYNC - -

Configuration enum EBR3.PDP16K_MODE.RSTMUX

Value F45B0
INV 1
RST -

Configuration enum EBR3.PDPSC16K_MODE.ADR0MUX

Value F37B0
ADR0 -
INV 1

Configuration enum EBR3.PDPSC16K_MODE.ADR1MUX

Value F39B0
ADR1 -
INV 1

Configuration enum EBR3.PDPSC16K_MODE.ADW0MUX

Value F10B0
ADW0 -
INV 1

Configuration enum EBR3.PDPSC16K_MODE.ADW1MUX

Value F9B0
ADW1 -
INV 1

Configuration enum EBR3.PDPSC16K_MODE.ADW2MUX

Value F13B0
ADW2 -
INV 1

Configuration enum EBR3.PDPSC16K_MODE.ADW3MUX

Value F12B0
ADW3 -
INV 1

Configuration enum EBR3.PDPSC16K_MODE.CLKMUX

clock inversion control for CLK

Value F8B0 F20B0 F35B0 F44B0
0 - - - -
CLK 1 - - 1
INV - 1 1 -

Configuration enum EBR3.PDPSC16K_MODE.DATA_WIDTH_R

data width of read port in PDPSC16K_MODE

Value F27B0 F29B0 F31B0 F33B0
X1 1 1 1 1
X18 - - - 1
X2 - 1 1 1
X32 - - - -
X36 - - - -
X4 - - 1 1
X9 - - 1 1

Configuration enum EBR3.PDPSC16K_MODE.DATA_WIDTH_W

data width of write port in PDPSC16K_MODE

Value F11B0 F14B0 F16B0 F19B0
X1 1 1 1 1
X18 - - - -
X2 - 1 1 1
X32 - - - -
X36 - - - -
X4 - - 1 1
X9 - - - 1

Configuration enum EBR3.PDPSC16K_MODE.OUTREG

extra output pipeline register enable/bypass

Value F15B0 F42B0
BYPASSED - -
USED 1 1

Configuration enum EBR3.PDPSC16K_MODE.RESETMODE

Value F24B0 F41B0
ASYNC 1 1
SYNC - -

Configuration enum EBR3.PDPSC16K_MODE.RSTMUX

Value F45B0
INV 1
RST -

Configuration enum EBR3.SP16K_MODE.AD0MUX

Value F10B0 F37B0
AD0 - -
INV 1 1

Configuration enum EBR3.SP16K_MODE.AD1MUX

Value F9B0 F39B0
AD1 - -
INV 1 1

Configuration enum EBR3.SP16K_MODE.AD2MUX

Value F13B0
AD2 -
INV 1

Configuration enum EBR3.SP16K_MODE.AD3MUX

Value F12B0
AD3 -
INV 1

Configuration enum EBR3.SP16K_MODE.CLKMUX

clock inversion control for CLK

Value F8B0 F20B0 F35B0 F44B0
0 - - - -
CLK 1 - - 1
INV - 1 1 -

Configuration enum EBR3.SP16K_MODE.DATA_WIDTH

data width of R/W port in SP16K_MODE

Value F11B0 F14B0 F16B0 F19B0 F27B0 F29B0 F31B0
X1 1 1 1 1 1 1 1
X18 - - - - - - -
X2 - 1 1 1 - 1 1
X4 - - 1 1 - - 1
X9 - - - 1 - - 1

Configuration enum EBR3.SP16K_MODE.OUTREG

extra output pipeline register enable/bypass

Value F15B0 F42B0
BYPASSED - -
USED 1 1

Configuration enum EBR3.SP16K_MODE.RESETMODE

Value F24B0 F41B0
ASYNC 1 1
SYNC - -

Configuration enum EBR3.SP16K_MODE.RSTMUX

Value F45B0
INV 1
RST -

Configuration enum EBR3.SP16K_MODE.WEMUX

Value F21B0
INV 1
WE -