EBR_1 Tile Documentation
Tile Bels
Config Bitmap
Configuration Words
Configuration word EBR0.DP16K_MODE.CSDECODE_B
port is enabled when CS inputs match this value
| EBR0.DP16K_MODE.CSDECODE_B[0] | F100B0 |
| EBR0.DP16K_MODE.CSDECODE_B[1] | F102B0 |
| EBR0.DP16K_MODE.CSDECODE_B[2] | F103B0 |
Configuration word EBR0.PDP16K_MODE.CSDECODE_R
port is enabled when CS inputs match this value
| EBR0.PDP16K_MODE.CSDECODE_R[0] | F100B0 |
| EBR0.PDP16K_MODE.CSDECODE_R[1] | F102B0 |
| EBR0.PDP16K_MODE.CSDECODE_R[2] | F103B0 |
Configuration word EBR0.PDPSC16K_MODE.CSDECODE_R
port is enabled when CS inputs match this value
| EBR0.PDPSC16K_MODE.CSDECODE_R[0] | F100B0 |
| EBR0.PDPSC16K_MODE.CSDECODE_R[1] | F102B0 |
| EBR0.PDPSC16K_MODE.CSDECODE_R[2] | F103B0 |
Configuration word EBR0.SP16K_MODE.CSDECODE
port is enabled when CS inputs match this value
| EBR0.SP16K_MODE.CSDECODE[0] | F100B0 |
| EBR0.SP16K_MODE.CSDECODE[1] | F102B0 |
| EBR0.SP16K_MODE.CSDECODE[2] | F103B0 |
Configuration Enums
Configuration enum EBR0.DP16K_MODE.ADA0MUX
Configuration enum EBR0.DP16K_MODE.ADA1MUX
Configuration enum EBR0.DP16K_MODE.ADA2MUX
Configuration enum EBR0.DP16K_MODE.ADA3MUX
Configuration enum EBR0.DP16K_MODE.ASYNC_RST_RELEASE_A
| Value |
F93B0 |
|---|
| ASYNC |
1 |
| SYNC |
- |
Configuration enum EBR0.DP16K_MODE.CEBMUX
Configuration enum EBR0.DP16K_MODE.CLKAMUX
clock inversion control for CLKA
| Value |
F81B0 |
F94B0 |
|---|
| 0 |
- |
- |
| CLKA |
1 |
- |
| INV |
- |
1 |
Configuration enum EBR0.DP16K_MODE.DATA_WIDTH_A
data width of port A in DP16K_MODE
| Value |
F84B0 |
F87B0 |
F89B0 |
F92B0 |
|---|
| X1 |
1 |
1 |
1 |
1 |
| X18 |
- |
- |
- |
- |
| X2 |
- |
1 |
1 |
1 |
| X4 |
- |
- |
1 |
1 |
| X9 |
- |
- |
- |
1 |
Configuration enum EBR0.DP16K_MODE.OUTREG_A
extra output pipeline register enable/bypass
| Value |
F88B0 |
|---|
| BYPASSED |
- |
| USED |
1 |
Configuration enum EBR0.DP16K_MODE.RESETMODE_A
| Value |
F101B0 |
|---|
| ASYNC |
1 |
| SYNC |
- |
Configuration enum EBR0.DP16K_MODE.WEAMUX
Configuration enum EBR0.FIFO16K_MODE.ASYNC_RST_RELEASE_A
| Value |
F93B0 |
|---|
| ASYNC |
1 |
| SYNC |
- |
Configuration enum EBR0.FIFO16K_MODE.CEBMUX
Configuration enum EBR0.FIFO16K_MODE.CKAMUX
clock inversion control for CKA
| Value |
F81B0 |
F94B0 |
|---|
| 0 |
- |
- |
| CKA |
1 |
- |
| INV |
- |
1 |
Configuration enum EBR0.FIFO16K_MODE.DATA_WIDTH_A
data width of port A in FIFO16K_MODE
| Value |
F84B0 |
F87B0 |
F89B0 |
F92B0 |
F95B0 |
|---|
| X1 |
1 |
1 |
1 |
1 |
1 |
| X18 |
- |
- |
- |
- |
1 |
| X2 |
- |
1 |
1 |
1 |
1 |
| X32 |
- |
- |
- |
- |
- |
| X36 |
- |
- |
- |
- |
- |
| X4 |
- |
- |
1 |
1 |
1 |
| X9 |
- |
- |
- |
1 |
1 |
Configuration enum EBR0.FIFO16K_MODE.OUTREG_A
extra output pipeline register enable/bypass
| Value |
F88B0 |
|---|
| BYPASSED |
- |
| USED |
1 |
Configuration enum EBR0.FIFO16K_MODE.RESETMODE_A
| Value |
F101B0 |
|---|
| ASYNC |
1 |
| SYNC |
- |
Configuration enum EBR0.GSR
if ENABLED, then read ports are reset by user GSR
| Value |
F91B0 |
|---|
| DISABLED |
1 |
| ENABLED |
- |
Configuration enum EBR0.MODE
EBR0 primitive mode
| Value |
F95B0 |
F99B0 |
|---|
| DP16K_MODE |
1 |
- |
| FIFO16K_MODE |
- |
1 |
| NONE |
- |
- |
| PDP16K_MODE |
- |
- |
| PDPSC16K_MODE |
- |
- |
| SP16K_MODE |
1 |
- |
Configuration enum EBR0.PDP16K_MODE.ADW0MUX
Configuration enum EBR0.PDP16K_MODE.ADW1MUX
Configuration enum EBR0.PDP16K_MODE.ADW2MUX
Configuration enum EBR0.PDP16K_MODE.ADW3MUX
Configuration enum EBR0.PDP16K_MODE.ASYNC_RST_RELEASE
| Value |
F93B0 |
|---|
| ASYNC |
1 |
| SYNC |
- |
Configuration enum EBR0.PDP16K_MODE.CERMUX
Configuration enum EBR0.PDP16K_MODE.CLKWMUX
clock inversion control for CLKW
| Value |
F81B0 |
F94B0 |
|---|
| 0 |
- |
- |
| CLKW |
1 |
- |
| INV |
- |
1 |
Configuration enum EBR0.PDP16K_MODE.DATA_WIDTH_W
data width of write port in PDP16K_MODE
| Value |
F84B0 |
F87B0 |
F89B0 |
F92B0 |
F95B0 |
|---|
| X1 |
1 |
1 |
1 |
1 |
1 |
| X18 |
- |
- |
- |
- |
1 |
| X2 |
- |
1 |
1 |
1 |
1 |
| X32 |
- |
- |
- |
- |
- |
| X36 |
- |
- |
- |
- |
- |
| X4 |
- |
- |
1 |
1 |
1 |
| X9 |
- |
- |
- |
1 |
1 |
Configuration enum EBR0.PDP16K_MODE.OUTREG
extra output pipeline register enable/bypass
| Value |
F88B0 |
|---|
| BYPASSED |
- |
| USED |
1 |
Configuration enum EBR0.PDP16K_MODE.RESETMODE
| Value |
F101B0 |
|---|
| ASYNC |
1 |
| SYNC |
- |
Configuration enum EBR0.PDPSC16K_MODE.ADW0MUX
Configuration enum EBR0.PDPSC16K_MODE.ADW1MUX
Configuration enum EBR0.PDPSC16K_MODE.ADW2MUX
Configuration enum EBR0.PDPSC16K_MODE.ADW3MUX
Configuration enum EBR0.PDPSC16K_MODE.ASYNC_RST_RELEASE
| Value |
F93B0 |
|---|
| ASYNC |
1 |
| SYNC |
- |
Configuration enum EBR0.PDPSC16K_MODE.CERMUX
Configuration enum EBR0.PDPSC16K_MODE.CLKMUX
clock inversion control for CLK
| Value |
F81B0 |
F94B0 |
|---|
| 0 |
- |
- |
| CLK |
1 |
- |
| INV |
- |
1 |
Configuration enum EBR0.PDPSC16K_MODE.DATA_WIDTH_W
data width of write port in PDPSC16K_MODE
| Value |
F84B0 |
F87B0 |
F89B0 |
F92B0 |
F95B0 |
|---|
| X1 |
1 |
1 |
1 |
1 |
1 |
| X18 |
- |
- |
- |
- |
1 |
| X2 |
- |
1 |
1 |
1 |
1 |
| X32 |
- |
- |
- |
- |
- |
| X36 |
- |
- |
- |
- |
- |
| X4 |
- |
- |
1 |
1 |
1 |
| X9 |
- |
- |
- |
1 |
1 |
Configuration enum EBR0.PDPSC16K_MODE.OUTREG
extra output pipeline register enable/bypass
| Value |
F88B0 |
|---|
| BYPASSED |
- |
| USED |
1 |
Configuration enum EBR0.PDPSC16K_MODE.RESETMODE
| Value |
F101B0 |
|---|
| ASYNC |
1 |
| SYNC |
- |
Configuration enum EBR0.SP16K_MODE.AD0MUX
Configuration enum EBR0.SP16K_MODE.AD1MUX
Configuration enum EBR0.SP16K_MODE.AD2MUX
Configuration enum EBR0.SP16K_MODE.AD3MUX
Configuration enum EBR0.SP16K_MODE.ASYNC_RST_RELEASE
| Value |
F93B0 |
|---|
| ASYNC |
1 |
| SYNC |
- |
Configuration enum EBR0.SP16K_MODE.CEMUX
Configuration enum EBR0.SP16K_MODE.CLKMUX
clock inversion control for CLK
| Value |
F81B0 |
F94B0 |
|---|
| 0 |
- |
- |
| CLK |
1 |
- |
| INV |
- |
1 |
Configuration enum EBR0.SP16K_MODE.DATA_WIDTH
data width of R/W port in SP16K_MODE
| Value |
F84B0 |
F87B0 |
F89B0 |
F92B0 |
|---|
| X1 |
1 |
1 |
1 |
1 |
| X18 |
- |
- |
- |
- |
| X2 |
- |
1 |
1 |
1 |
| X4 |
- |
- |
1 |
1 |
| X9 |
- |
- |
- |
1 |
Configuration enum EBR0.SP16K_MODE.OUTREG
extra output pipeline register enable/bypass
| Value |
F88B0 |
|---|
| BYPASSED |
- |
| USED |
1 |
Configuration enum EBR0.SP16K_MODE.RESETMODE
| Value |
F101B0 |
|---|
| ASYNC |
1 |
| SYNC |
- |
Configuration enum EBR0.SP16K_MODE.WEMUX
Fixed Connections
| Source | | Sink |
|---|
| N1W1:JDOA4_EBR_CORE | → |
N1:JF0 |
| N1W1:JDOA5_EBR_CORE | → |
N1:JF1 |
| N1W1:JDOA6_EBR_CORE | → |
N1:JF2 |
| N1W1:JDOA7_EBR_CORE | → |
N1:JF3 |
| N1W1:JDOA8_EBR_CORE | → |
N1:JF4 |
| N1W1:JDOA9_EBR_CORE | → |
N1:JF5 |
| N1W1:JDOA10_EBR_CORE | → |
N1:JF6 |
| N1W1:JDOA11_EBR_CORE | → |
N1:JF7 |
| N1W1:JDOB4_EBR_CORE | → |
N1:JQ0 |
| N1W1:JDOB5_EBR_CORE | → |
N1:JQ1 |
| N1W1:JDOB6_EBR_CORE | → |
N1:JQ2 |
| N1W1:JDOB7_EBR_CORE | → |
N1:JQ3 |
| N1W1:JDOB8_EBR_CORE | → |
N1:JQ4 |
| N1W1:JDOB9_EBR_CORE | → |
N1:JQ5 |
| N1W1:JDOB10_EBR_CORE | → |
N1:JQ6 |
| N1W1:JDOB11_EBR_CORE | → |
N1:JQ7 |
| N1W1:JDOA12_EBR_CORE | → |
N1E1:JF0 |
| N1W1:JDOA13_EBR_CORE | → |
N1E1:JF1 |
| N1W1:JDOA14_EBR_CORE | → |
N1E1:JF2 |
| N1W1:JDOA15_EBR_CORE | → |
N1E1:JF3 |
| N1W1:JDOA16_EBR_CORE | → |
N1E1:JF4 |
| N1W1:JDOA17_EBR_CORE | → |
N1E1:JF5 |
| N1W1:JDOB12_EBR_CORE | → |
N1E1:JQ0 |
| N1W1:JDOB13_EBR_CORE | → |
N1E1:JQ1 |
| N1W1:JDOB14_EBR_CORE | → |
N1E1:JQ2 |
| N1W1:JDOB15_EBR_CORE | → |
N1E1:JQ3 |
| N1W1:JDOB16_EBR_CORE | → |
N1E1:JQ4 |
| N1W1:JDOB17_EBR_CORE | → |
N1E1:JQ5 |
| N1E1:JCIBMUXOUTA3 | → |
N1W1:JADA0_EBR_CORE |
| N1W1:JCIBMUXOUTD7 | → |
N1W1:JADA10_EBR_CORE |
| N1W1:JCIBMUXOUTA5 | → |
N1W1:JADA11_EBR_CORE |
| N1W1:JCIBMUXOUTC7 | → |
N1W1:JADA12_EBR_CORE |
| N1W1:JCIBMUXOUTB3 | → |
N1W1:JADA13_EBR_CORE |
| N1E1:JCIBMUXOUTA5 | → |
N1W1:JADA1_EBR_CORE |
| N1E1:JCIBMUXOUTB1 | → |
N1W1:JADA2_EBR_CORE |
| N1E1:JCIBMUXOUTB6 | → |
N1W1:JADA3_EBR_CORE |
| N1W1:JCIBMUXOUTD0 | → |
N1W1:JADA4_EBR_CORE |
| N1W1:JCIBMUXOUTB1 | → |
N1W1:JADA5_EBR_CORE |
| N1W1:JCIBMUXOUTD6 | → |
N1W1:JADA6_EBR_CORE |
| N1W1:JCIBMUXOUTB7 | → |
N1W1:JADA7_EBR_CORE |
| N1W1:JCIBMUXOUTD1 | → |
N1W1:JADA8_EBR_CORE |
| N1W1:JCIBMUXOUTA1 | → |
N1W1:JADA9_EBR_CORE |
| N1E1:JCIBMUXOUTC6 | → |
N1W1:JADB0_EBR_CORE |
| N1W1:JCIBMUXOUTD5 | → |
N1W1:JADB10_EBR_CORE |
| N1:JCIBMUXOUTA7 | → |
N1W1:JADB11_EBR_CORE |
| N1:JCIBMUXOUTC7 | → |
N1W1:JADB12_EBR_CORE |
| N1:JCIBMUXOUTB3 | → |
N1W1:JADB13_EBR_CORE |
| N1E1:JCIBMUXOUTC7 | → |
N1W1:JADB1_EBR_CORE |
| N1E1:JCIBMUXOUTD0 | → |
N1W1:JADB2_EBR_CORE |
| N1E1:JCIBMUXOUTD1 | → |
N1W1:JADB3_EBR_CORE |
| N1:JCIBMUXOUTD0 | → |
N1W1:JADB4_EBR_CORE |
| N1W1:JCIBMUXOUTB2 | → |
N1W1:JADB5_EBR_CORE |
| N1W1:JCIBMUXOUTD4 | → |
N1W1:JADB6_EBR_CORE |
| N1:JCIBMUXOUTB7 | → |
N1W1:JADB7_EBR_CORE |
| N1:JCIBMUXOUTD1 | → |
N1W1:JADB8_EBR_CORE |
| N1W1:JCIBMUXOUTA2 | → |
N1W1:JADB9_EBR_CORE |
| N1W1:JCE0 | → |
N1W1:JCEA_EBR_CORE |
| N1:JCE0 | → |
N1W1:JCEB_EBR_CORE |
| N1E1:JCLK0 | → |
N1W1:JCLKA_EBR_CORE |
| N1E1:JCLK1 | → |
N1W1:JCLKB_EBR_CORE |
| N1W1:JCE1 | → |
N1W1:JCSA0_EBR_CORE |
| N1W1:JCLK1 | → |
N1W1:JCSA1_EBR_CORE |
| N1E1:JCE1 | → |
N1W1:JCSA2_EBR_CORE |
| N1:JCE1 | → |
N1W1:JCSB0_EBR_CORE |
| N1:JCLK1 | → |
N1W1:JCSB1_EBR_CORE |
| N1E1:JLSR1 | → |
N1W1:JCSB2_EBR_CORE |
| N1W1:JCIBMUXOUTA4 | → |
N1W1:JDIA0_EBR_CORE |
| N1:JCIBMUXOUTA6 | → |
N1W1:JDIA10_EBR_CORE |
| N1:JCIBMUXOUTB6 | → |
N1W1:JDIA11_EBR_CORE |
| N1E1:JCIBMUXOUTB0 | → |
N1W1:JDIA12_EBR_CORE |
| N1E1:JCIBMUXOUTA0 | → |
N1W1:JDIA13_EBR_CORE |
| N1E1:JCIBMUXOUTB2 | → |
N1W1:JDIA14_EBR_CORE |
| N1E1:JCIBMUXOUTA2 | → |
N1W1:JDIA15_EBR_CORE |
| N1E1:JCIBMUXOUTA4 | → |
N1W1:JDIA16_EBR_CORE |
| N1E1:JCIBMUXOUTB4 | → |
N1W1:JDIA17_EBR_CORE |
| N1W1:JCIBMUXOUTB4 | → |
N1W1:JDIA1_EBR_CORE |
| N1W1:JCIBMUXOUTA6 | → |
N1W1:JDIA2_EBR_CORE |
| N1W1:JCIBMUXOUTB6 | → |
N1W1:JDIA3_EBR_CORE |
| N1:JCIBMUXOUTB0 | → |
N1W1:JDIA4_EBR_CORE |
| N1:JCIBMUXOUTA0 | → |
N1W1:JDIA5_EBR_CORE |
| N1:JCIBMUXOUTB2 | → |
N1W1:JDIA6_EBR_CORE |
| N1:JCIBMUXOUTA2 | → |
N1W1:JDIA7_EBR_CORE |
| N1:JCIBMUXOUTA4 | → |
N1W1:JDIA8_EBR_CORE |
| N1:JCIBMUXOUTB4 | → |
N1W1:JDIA9_EBR_CORE |
| N1W1:JCIBMUXOUTD2 | → |
N1W1:JDIB0_EBR_CORE |
| N1:JCIBMUXOUTC3 | → |
N1W1:JDIB10_EBR_CORE |
| N1:JCIBMUXOUTD3 | → |
N1W1:JDIB11_EBR_CORE |
| N1E1:JCIBMUXOUTC4 | → |
N1W1:JDIB12_EBR_CORE |
| N1E1:JCIBMUXOUTD4 | → |
N1W1:JDIB13_EBR_CORE |
| N1E1:JCIBMUXOUTD5 | → |
N1W1:JDIB14_EBR_CORE |
| N1E1:JCIBMUXOUTC5 | → |
N1W1:JDIB15_EBR_CORE |
| N1E1:JCIBMUXOUTD2 | → |
N1W1:JDIB16_EBR_CORE |
| N1E1:JCIBMUXOUTC2 | → |
N1W1:JDIB17_EBR_CORE |
| N1W1:JCIBMUXOUTC2 | → |
N1W1:JDIB1_EBR_CORE |
| N1W1:JCIBMUXOUTC3 | → |
N1W1:JDIB2_EBR_CORE |
| N1W1:JCIBMUXOUTD3 | → |
N1W1:JDIB3_EBR_CORE |
| N1:JCIBMUXOUTC4 | → |
N1W1:JDIB4_EBR_CORE |
| N1:JCIBMUXOUTD4 | → |
N1W1:JDIB5_EBR_CORE |
| N1:JCIBMUXOUTD5 | → |
N1W1:JDIB6_EBR_CORE |
| N1:JCIBMUXOUTC5 | → |
N1W1:JDIB7_EBR_CORE |
| N1:JCIBMUXOUTD2 | → |
N1W1:JDIB8_EBR_CORE |
| N1:JCIBMUXOUTC2 | → |
N1W1:JDIB9_EBR_CORE |
| N1:JCIBMUXOUTA1 | → |
N1W1:JDWS0_EBR_CORE |
| N1:JCIBMUXOUTA5 | → |
N1W1:JDWS1_EBR_CORE |
| N1:JCIBMUXOUTC6 | → |
N1W1:JDWS2_EBR_CORE |
| N1:JCIBMUXOUTB5 | → |
N1W1:JDWS3_EBR_CORE |
| N1:JCIBMUXOUTC0 | → |
N1W1:JDWS4_EBR_CORE |
| N1W1:JONEERR_EBR_CORE | → |
N1W1:JF0 |
| N1W1:JTWOERR_EBR_CORE | → |
N1W1:JF1 |
| N1W1:JDOA0_EBR_CORE | → |
N1W1:JF4 |
| N1W1:JDOA1_EBR_CORE | → |
N1W1:JF5 |
| N1W1:JDOA2_EBR_CORE | → |
N1W1:JF6 |
| N1W1:JDOA3_EBR_CORE | → |
N1W1:JF7 |
| N1W1:JEMPTYF_EBR_CORE | → |
N1W1:JQ0 |
| N1W1:JFULLF_EBR_CORE | → |
N1W1:JQ1 |
| N1W1:JAEMPTY_EBR_CORE | → |
N1W1:JQ2 |
| N1W1:JAFULL_EBR_CORE | → |
N1W1:JQ3 |
| N1W1:JDOB0_EBR_CORE | → |
N1W1:JQ4 |
| N1W1:JDOB1_EBR_CORE | → |
N1W1:JQ5 |
| N1W1:JDOB2_EBR_CORE | → |
N1W1:JQ6 |
| N1W1:JDOB3_EBR_CORE | → |
N1W1:JQ7 |
| N1W1:JLSR0 | → |
N1W1:JRSTA_EBR_CORE |
| N1:JLSR0 | → |
N1W1:JRSTB_EBR_CORE |
| N1W1:JLSR1 | → |
N1W1:JWEA_EBR_CORE |
| N1:JLSR1 | → |
N1W1:JWEB_EBR_CORE |