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E |
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P |
C |
C |
C |
C |
C |
C |
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M |
O |
E |
R |
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R |
R |
R |
R |
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S |
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E |
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M |
C |
C |
C |
C |
M |
R |
R |
R |
R |
R |
S |
E |
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A
is signed in SIGNEDSTATIC_EN
mode
Value | F59B0 |
---|---|
DISABLED | - |
ENABLED | 1 |
selects between actually doing 9x9 mult; or just passing through inputs
Value | F60B0 |
---|---|
BYPASS | 1 |
USED | - |
CEA gating and inversion control
Value | F61B0 | F62B0 |
---|---|---|
1 | 1 | 1 |
CEA | - | - |
INV | - | 1 |
clock gating and inversion control
Value | F63B0 | F64B0 |
---|---|---|
0 | - | - |
CLK | 1 | - |
INV | 1 | 1 |
if ENABLED
primitive is reset by user GSR
Value | F65B0 |
---|---|
DISABLED | 0 |
ENABLED | 1 |
MULT9_L3 primitive mode
Value | F65B0 | F69B0 |
---|---|---|
MULT9_CORE | - | - |
NONE | 1 | 1 |
register enable or bypass for A1
Value | F66B0 |
---|---|
BYPASS | 1 |
REGISTER | - |
register enable or bypass for A2
Value | F67B0 |
---|---|
BYPASS | 1 |
REGISTER | - |
register enable or bypass for B
Value | F68B0 |
---|---|
BYPASS | 1 |
REGISTER | - |
RSTA gating and inversion control
Value | F69B0 | F70B0 |
---|---|---|
0 | - | - |
INV | 1 | 1 |
RSTA | 1 | - |
use shift register for A
Value | F71B0 |
---|---|
DISABLED | - |
ENABLED | 1 |
A
signedness from SIGNEDSTATIC_EN
(when ENABLED
) or ASIGNED
input
Value | F72B0 |
---|---|
DISABLED | - |
ENABLED | 1 |
use 18-bit shift register for A
Value | F58B0 |
---|---|
DISABLED | - |
ENABLED | 1 |
B
signedness in SIGNEDSTATIC_EN
mode
Value | F31B0 |
---|---|
DISABLED | - |
ENABLED | 1 |
selects between pre-adder in datapath; or just passing through inputs
Value | F32B0 |
---|---|
BYPASS | 1 |
USED | - |
CEB gating and inversion control
Value | F33B0 | F34B0 |
---|---|---|
1 | 1 | 1 |
CEB | - | - |
INV | - | 1 |
CECL gating and inversion control
Value | F35B0 | F36B0 |
---|---|---|
1 | 1 | 1 |
CECL | - | - |
INV | - | 1 |
clock gating and inversion control
Value | F37B0 | F38B0 |
---|---|---|
0 | - | - |
CLK | 1 | - |
INV | 1 | 1 |
C
signedness in SIGNEDSTATIC_EN
mode
Value | F39B0 |
---|---|
DISABLED | - |
ENABLED | 1 |
if ENABLED
primitive is reset by user GSR
Value | F40B0 |
---|---|
DISABLED | 0 |
ENABLED | 1 |
PREADD9_L3 primitive mode
Value | F40B0 | F46B0 | F48B0 |
---|---|---|---|
NONE | 1 | 1 | 1 |
PREADD9_CORE | - | - | - |
selects 2nd pre-adder operand
Value | F41B0 |
---|---|
INPUT_B_AS_PREADDER_OPERAND | - |
INPUT_C_AS_PREADDER_OPERAND | 1 |
enable pre-adder carry cascade
Value | F42B0 |
---|---|
DISABLED | - |
ENABLED | 1 |
register enable or bypass for BL
Value | F43B0 |
---|---|
BYPASS | 1 |
REGISTER | - |
register enable or bypass for BR0
Value | F44B0 |
---|---|
BYPASS | 1 |
REGISTER | - |
register enable or bypass for BR1
Value | F45B0 |
---|---|
BYPASS | 1 |
REGISTER | - |
RSTB gating and inversion control
Value | F46B0 | F47B0 |
---|---|---|
0 | - | - |
INV | 1 | 1 |
RSTB | 1 | - |
RSTCL gating and inversion control
Value | F48B0 | F49B0 |
---|---|---|
0 | - | - |
INV | 1 | 1 |
RSTCL | 1 | - |
use left shift register for B
Value | F50B0 |
---|---|
BYPASS | 1 |
REGISTER | - |
use right shift register for B
Value | F51B0 |
---|---|
BYPASS | 1 |
REGISTER | - |
B
and C
signedness from parameters (ENABLED
) or inputs
Value | F52B0 |
---|---|
DISABLED | - |
ENABLED | 1 |
use 18-bit shift register for B
Value | F30B0 |
---|---|
DISABLED | - |
ENABLED | 1 |
preadder function
Value | F53B0 |
---|---|
ADDITION | 1 |
SUBTRACTION | - |