DSP_R_9 Tile Documentation

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Configuration Enums

Configuration enum MULT9_L3.ASIGNED_OPERAND_EN

A is signed in SIGNEDSTATIC_EN mode

Value F59B0
DISABLED -
ENABLED 1

Configuration enum MULT9_L3.BYPASS_MULT9

selects between actually doing 9x9 mult; or just passing through inputs

Value F60B0
BYPASS 1
USED -

Configuration enum MULT9_L3.CEAMUX

CEA gating and inversion control

Value F61B0 F62B0
1 1 1
CEA - -
INV - 1

Configuration enum MULT9_L3.CLKMUX

clock gating and inversion control

Value F63B0 F64B0
0 - -
CLK 1 -
INV 1 1

Configuration enum MULT9_L3.GSR

if ENABLED primitive is reset by user GSR

Value F65B0
DISABLED 0
ENABLED 1

Configuration enum MULT9_L3.MODE

MULT9_L3 primitive mode

Value F65B0 F69B0
MULT9_CORE - -
NONE 1 1

Configuration enum MULT9_L3.REGBYPSA1

register enable or bypass for A1

Value F66B0
BYPASS 1
REGISTER -

Configuration enum MULT9_L3.REGBYPSA2

register enable or bypass for A2

Value F67B0
BYPASS 1
REGISTER -

Configuration enum MULT9_L3.REGBYPSB

register enable or bypass for B

Value F68B0
BYPASS 1
REGISTER -

Configuration enum MULT9_L3.RSTAMUX

RSTA gating and inversion control

Value F69B0 F70B0
0 - -
INV 1 1
RSTA 1 -

Configuration enum MULT9_L3.SHIFTA

use shift register for A

Value F71B0
DISABLED -
ENABLED 1

Configuration enum MULT9_L3.SIGNEDSTATIC_EN

A signedness from SIGNEDSTATIC_EN (when ENABLED) or ASIGNED input

Value F72B0
DISABLED -
ENABLED 1

Configuration enum MULT9_L3.SR_18BITSHIFT_EN

use 18-bit shift register for A

Value F58B0
DISABLED -
ENABLED 1

Configuration enum PREADD9_L3.BSIGNED_OPERAND_EN

B signedness in SIGNEDSTATIC_EN mode

Value F31B0
DISABLED -
ENABLED 1

Configuration enum PREADD9_L3.BYPASS_PREADD9

selects between pre-adder in datapath; or just passing through inputs

Value F32B0
BYPASS 1
USED -

Configuration enum PREADD9_L3.CEBMUX

CEB gating and inversion control

Value F33B0 F34B0
1 1 1
CEB - -
INV - 1

Configuration enum PREADD9_L3.CECLMUX

CECL gating and inversion control

Value F35B0 F36B0
1 1 1
CECL - -
INV - 1

Configuration enum PREADD9_L3.CLKMUX

clock gating and inversion control

Value F37B0 F38B0
0 - -
CLK 1 -
INV 1 1

Configuration enum PREADD9_L3.CSIGNED

C signedness in SIGNEDSTATIC_EN mode

Value F39B0
DISABLED -
ENABLED 1

Configuration enum PREADD9_L3.GSR

if ENABLED primitive is reset by user GSR

Value F40B0
DISABLED 0
ENABLED 1

Configuration enum PREADD9_L3.MODE

PREADD9_L3 primitive mode

Value F40B0 F46B0 F48B0
NONE 1 1 1
PREADD9_CORE - - -

Configuration enum PREADD9_L3.OPC

selects 2nd pre-adder operand

Value F41B0
INPUT_B_AS_PREADDER_OPERAND -
INPUT_C_AS_PREADDER_OPERAND 1

Configuration enum PREADD9_L3.PREADDCAS_EN

enable pre-adder carry cascade

Value F42B0
DISABLED -
ENABLED 1

Configuration enum PREADD9_L3.REGBYPSBL

register enable or bypass for BL

Value F43B0
BYPASS 1
REGISTER -

Configuration enum PREADD9_L3.REGBYPSBR0

register enable or bypass for BR0

Value F44B0
BYPASS 1
REGISTER -

Configuration enum PREADD9_L3.REGBYPSBR1

register enable or bypass for BR1

Value F45B0
BYPASS 1
REGISTER -

Configuration enum PREADD9_L3.RSTBMUX

RSTB gating and inversion control

Value F46B0 F47B0
0 - -
INV 1 1
RSTB 1 -

Configuration enum PREADD9_L3.RSTCLMUX

RSTCL gating and inversion control

Value F48B0 F49B0
0 - -
INV 1 1
RSTCL 1 -

Configuration enum PREADD9_L3.SHIFTBL

use left shift register for B

Value F50B0
BYPASS 1
REGISTER -

Configuration enum PREADD9_L3.SHIFTBR

use right shift register for B

Value F51B0
BYPASS 1
REGISTER -

Configuration enum PREADD9_L3.SIGNEDSTATIC_EN

B and C signedness from parameters (ENABLED) or inputs

Value F52B0
DISABLED -
ENABLED 1

Configuration enum PREADD9_L3.SR_18BITSHIFT_EN

use 18-bit shift register for B

Value F30B0
DISABLED -
ENABLED 1

Configuration enum PREADD9_L3.SUBSTRACT_EN

preadder function

Value F53B0
ADDITION 1
SUBTRACTION -