DSP_R_8 Tile Documentation

Config Bitmap

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Configuration Enums

Configuration enum ACC54_1.GSR

if ENABLED primitive is reset by user GSR

Value F51B0
DISABLED -
ENABLED 1

Configuration enum ACC54_1.LOADREGBYPS1

LOAD register 1 enable or bypass

Value F52B0
BYPASS 1
REGISTER -

Configuration enum ACC54_1.LOADREGBYPS2

LOAD register 2 enable or bypass

Value F53B0
BYPASS 1
REGISTER -

Configuration enum ACC54_1.LOADREGBYPS3

LOAD register 3 enable or bypass

Value F54B0
BYPASS 1
REGISTER -

Configuration enum ACC54_1.M9ADDSUBREGBYPS1

M9ADDSUB register 1 enable or bypass

Value F57B0
BYPASS 1
REGISTER -

Configuration enum ACC54_1.M9ADDSUBREGBYPS2

M9ADDSUB register 2 enable or bypass

Value F58B0
BYPASS 1
REGISTER -

Configuration enum ACC54_1.M9ADDSUBREGBYPS3

M9ADDSUB register 3 enable or bypass

Value F59B0
BYPASS 1
REGISTER -

Configuration enum ACC54_1.M9ADDSUB_CTRL

select stage 1 operation in static opcode mode

Value F55B0 F56B0
ADDITION - -
ADDSUB 1 -
SUBADD - 1
SUBTRACTION 1 1

Configuration enum ACC54_1.OUTREGBYPS

output register enable or bypass

Value F60B0
BYPASS 1
REGISTER -

Configuration enum MULT9_H2.ASIGNED_OPERAND_EN

A is signed in SIGNEDSTATIC_EN mode

Value F29B0
DISABLED -
ENABLED 1

Configuration enum MULT9_H2.BYPASS_MULT9

selects between actually doing 9x9 mult; or just passing through inputs

Value F30B0
BYPASS 1
USED -

Configuration enum MULT9_H2.CEAMUX

CEA gating and inversion control

Value F31B0 F32B0
1 1 1
CEA - -
INV - 1

Configuration enum MULT9_H2.CLKMUX

clock gating and inversion control

Value F33B0 F34B0
0 - -
CLK 1 -
INV 1 1

Configuration enum MULT9_H2.GSR

if ENABLED primitive is reset by user GSR

Value F35B0
DISABLED 0
ENABLED 1

Configuration enum MULT9_H2.MODE

MULT9_H2 primitive mode

Value F35B0 F39B0
MULT9_CORE - -
NONE 1 1

Configuration enum MULT9_H2.REGBYPSA1

register enable or bypass for A1

Value F36B0
BYPASS 1
REGISTER -

Configuration enum MULT9_H2.REGBYPSA2

register enable or bypass for A2

Value F37B0
BYPASS 1
REGISTER -

Configuration enum MULT9_H2.REGBYPSB

register enable or bypass for B

Value F38B0
BYPASS 1
REGISTER -

Configuration enum MULT9_H2.RSTAMUX

RSTA gating and inversion control

Value F39B0 F40B0
0 - -
INV 1 1
RSTA 1 -

Configuration enum MULT9_H2.SHIFTA

use shift register for A

Value F41B0
DISABLED -
ENABLED 1

Configuration enum MULT9_H2.SIGNEDSTATIC_EN

A signedness from SIGNEDSTATIC_EN (when ENABLED) or ASIGNED input

Value F42B0
DISABLED -
ENABLED 1

Configuration enum MULT9_H2.SR_18BITSHIFT_EN

use 18-bit shift register for A

Value F28B0
DISABLED -
ENABLED 1

Configuration enum PREADD9_H2.BSIGNED_OPERAND_EN

B signedness in SIGNEDSTATIC_EN mode

Value F1B0
DISABLED -
ENABLED 1

Configuration enum PREADD9_H2.BYPASS_PREADD9

selects between pre-adder in datapath; or just passing through inputs

Value F2B0
BYPASS 1
USED -

Configuration enum PREADD9_H2.CEBMUX

CEB gating and inversion control

Value F3B0 F4B0
1 1 1
CEB - -
INV - 1

Configuration enum PREADD9_H2.CECLMUX

CECL gating and inversion control

Value F5B0 F6B0
1 1 1
CECL - -
INV - 1

Configuration enum PREADD9_H2.CLKMUX

clock gating and inversion control

Value F7B0 F8B0
0 - -
CLK 1 -
INV 1 1

Configuration enum PREADD9_H2.CSIGNED

C signedness in SIGNEDSTATIC_EN mode

Value F9B0
DISABLED -
ENABLED 1

Configuration enum PREADD9_H2.GSR

if ENABLED primitive is reset by user GSR

Value F10B0
DISABLED 0
ENABLED 1

Configuration enum PREADD9_H2.MODE

PREADD9_H2 primitive mode

Value F10B0 F16B0 F18B0
NONE 1 1 1
PREADD9_CORE - - -

Configuration enum PREADD9_H2.OPC

selects 2nd pre-adder operand

Value F11B0
INPUT_B_AS_PREADDER_OPERAND -
INPUT_C_AS_PREADDER_OPERAND 1

Configuration enum PREADD9_H2.PREADDCAS_EN

enable pre-adder carry cascade

Value F12B0
DISABLED -
ENABLED 1

Configuration enum PREADD9_H2.REGBYPSBL

register enable or bypass for BL

Value F13B0
BYPASS 1
REGISTER -

Configuration enum PREADD9_H2.REGBYPSBR0

register enable or bypass for BR0

Value F14B0
BYPASS 1
REGISTER -

Configuration enum PREADD9_H2.REGBYPSBR1

register enable or bypass for BR1

Value F15B0
BYPASS 1
REGISTER -

Configuration enum PREADD9_H2.RSTBMUX

RSTB gating and inversion control

Value F16B0 F17B0
0 - -
INV 1 1
RSTB 1 -

Configuration enum PREADD9_H2.RSTCLMUX

RSTCL gating and inversion control

Value F18B0 F19B0
0 - -
INV 1 1
RSTCL 1 -

Configuration enum PREADD9_H2.SHIFTBL

use left shift register for B

Value F20B0
BYPASS 1
REGISTER -

Configuration enum PREADD9_H2.SHIFTBR

use right shift register for B

Value F21B0
BYPASS 1
REGISTER -

Configuration enum PREADD9_H2.SIGNEDSTATIC_EN

B and C signedness from parameters (ENABLED) or inputs

Value F22B0
DISABLED -
ENABLED 1

Configuration enum PREADD9_H2.SR_18BITSHIFT_EN

use 18-bit shift register for B

Value F0B0
DISABLED -
ENABLED 1

Configuration enum PREADD9_H2.SUBSTRACT_EN

preadder function

Value F23B0
ADDITION 1
SUBTRACTION -

Configuration enum REG18_H0_1.CEPMUX

CEP gating and inversion control

Value F85B0 F86B0
1 1 1
CEP - -
INV - 1

Configuration enum REG18_H0_1.CLKMUX

clock gating and inversion control

Value F87B0 F88B0
0 - -
CLK 1 -
INV 1 1

Configuration enum REG18_H0_1.GSR

if ENABLED primitive is reset by user GSR

Value F89B0
DISABLED 0
ENABLED 1

Configuration enum REG18_H0_1.MODE

REG18_H0_1 primitive mode

Value F89B0 F91B0
NONE 1 1
REG18_CORE - -

Configuration enum REG18_H0_1.REGBYPS

register enable or bypass

Value F90B0
BYPASS 1
REGISTER -

Configuration enum REG18_H0_1.RSTPMUX

RSTP gating and inversion control

Value F91B0 F92B0
0 - -
INV 1 1
RSTP 1 -