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E |
E |
P |
C |
C |
C |
C |
C |
C |
C |
M |
O |
E |
R |
R |
R |
R |
R |
R |
R |
S |
S |
E |
E |
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E |
E |
M |
C |
C |
C |
C |
M |
R |
R |
R |
R |
R |
S |
E |
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C |
C |
C |
C |
M |
R |
R |
R |
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A |
M |
A |
A |
A |
C |
C |
A |
A |
A |
C |
C |
C |
C |
C |
C |
C |
C |
C |
C |
C |
C |
C |
C |
D |
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cascade carry of two ACC54s to create a 108-bit accumulator
| Value | F60B0 |
|---|---|
| BYPASSCASCADE | - |
| CASCADE2ACCU54TOFORMACCU108 | 1 |
accumulator bypass
| Value | F61B0 |
|---|---|
| BYPASS | 1 |
| USED | - |
accumulator mode
| Value | F62B0 | F63B0 | F64B0 |
|---|---|---|---|
| MODE0 | - | - | - |
| MODE1 | 1 | - | - |
| MODE2 | - | 1 | - |
| MODE3 | 1 | 1 | - |
| MODE4 | - | - | 1 |
| MODE5 | 1 | - | 1 |
| MODE6 | - | 1 | 1 |
| MODE7 | 1 | 1 | 1 |
ADDSUBSIGN register 1 enable or bypass
| Value | F67B0 |
|---|---|
| BYPASS | 1 |
| REGISTER | - |
ADDSUBSIGN register 2 enable or bypass
| Value | F68B0 |
|---|---|
| BYPASS | 1 |
| REGISTER | - |
ADDSUBSIGN register 3 enable or bypass
| Value | F69B0 |
|---|---|
| BYPASS | 1 |
| REGISTER | - |
select stage 2 operation in static opcode mode
| Value | F65B0 | F66B0 |
|---|---|---|
| ADD_ADD_CTRL_54_BIT_ADDER | - | - |
| ADD_SUB_CTRL_54_BIT_ADDER | - | 1 |
| SUB_ADD_CTRL_54_BIT_ADDER | 1 | - |
| SUB_SUB_CTRL_54_BIT_ADDER | 1 | 1 |
cascade output register enable or bypass
| Value | F70B0 |
|---|---|
| BYPASS | 1 |
| REGISTER | - |
CEC gating and inversion control
| Value | F71B0 | F72B0 |
|---|---|---|
| 1 | 1 | 1 |
| CEC | - | - |
| INV | - | 1 |
CEO gating and inversion control
| Value | F73B0 | F74B0 |
|---|---|---|
| 1 | 1 | 1 |
| CEO | - | - |
| INV | - | 1 |
CIN register 1 enable or bypass
| Value | F75B0 |
|---|---|
| BYPASS | 1 |
| REGISTER | - |
CIN register 2 enable or bypass
| Value | F76B0 |
|---|---|
| BYPASS | 1 |
| REGISTER | - |
CIN register 3 enable or bypass
| Value | F77B0 |
|---|---|
| BYPASS | 1 |
| REGISTER | - |
clock gating and inversion control
| Value | F78B0 | F79B0 |
|---|---|---|
| 0 | - | - |
| CLK | 1 | - |
| INV | 1 | 1 |
if SELECT then use PROGCONST for C operand
| Value | F80B0 |
|---|---|
| BYPASS | - |
| SELECT | 1 |
C register 1 enable or bypass
| Value | F81B0 |
|---|---|
| BYPASS | 1 |
| REGISTER | - |
C register 2 enable or bypass
| Value | F82B0 |
|---|---|
| BYPASS | 1 |
| REGISTER | - |
C register 3 enable or bypass
| Value | F83B0 |
|---|---|
| BYPASS | 1 |
| REGISTER | - |
enable DSP cascading
| Value | F84B0 |
|---|---|
| DISABLED | - |
| ENABLED | 1 |
ACC54_0 primitive mode
| Value | F61B0 |
|---|---|
| ACC54_CORE | - |
| NONE | 1 |
A is signed in SIGNEDSTATIC_EN mode
| Value | F29B0 |
|---|---|
| DISABLED | - |
| ENABLED | 1 |
selects between actually doing 9x9 mult; or just passing through inputs
| Value | F30B0 |
|---|---|
| BYPASS | 1 |
| USED | - |
CEA gating and inversion control
| Value | F31B0 | F32B0 |
|---|---|---|
| 1 | 1 | 1 |
| CEA | - | - |
| INV | - | 1 |
clock gating and inversion control
| Value | F33B0 | F34B0 |
|---|---|---|
| 0 | - | - |
| CLK | 1 | - |
| INV | 1 | 1 |
if ENABLED primitive is reset by user GSR
| Value | F35B0 |
|---|---|
| DISABLED | 0 |
| ENABLED | 1 |
MULT9_L0 primitive mode
| Value | F35B0 | F39B0 |
|---|---|---|
| MULT9_CORE | - | - |
| NONE | 1 | 1 |
register enable or bypass for A1
| Value | F36B0 |
|---|---|
| BYPASS | 1 |
| REGISTER | - |
register enable or bypass for A2
| Value | F37B0 |
|---|---|
| BYPASS | 1 |
| REGISTER | - |
register enable or bypass for B
| Value | F38B0 |
|---|---|
| BYPASS | 1 |
| REGISTER | - |
RSTA gating and inversion control
| Value | F39B0 | F40B0 |
|---|---|---|
| 0 | - | - |
| INV | 1 | 1 |
| RSTA | 1 | - |
use shift register for A
| Value | F41B0 |
|---|---|
| DISABLED | - |
| ENABLED | 1 |
A signedness from SIGNEDSTATIC_EN (when ENABLED) or ASIGNED input
| Value | F42B0 |
|---|---|
| DISABLED | - |
| ENABLED | 1 |
use 18-bit shift register for A
| Value | F28B0 |
|---|---|
| DISABLED | - |
| ENABLED | 1 |
B signedness in SIGNEDSTATIC_EN mode
| Value | F1B0 |
|---|---|
| DISABLED | - |
| ENABLED | 1 |
selects between pre-adder in datapath; or just passing through inputs
| Value | F2B0 |
|---|---|
| BYPASS | 1 |
| USED | - |
CEB gating and inversion control
| Value | F3B0 | F4B0 |
|---|---|---|
| 1 | 1 | 1 |
| CEB | - | - |
| INV | - | 1 |
CECL gating and inversion control
| Value | F5B0 | F6B0 |
|---|---|---|
| 1 | 1 | 1 |
| CECL | - | - |
| INV | - | 1 |
clock gating and inversion control
| Value | F7B0 | F8B0 |
|---|---|---|
| 0 | - | - |
| CLK | 1 | - |
| INV | 1 | 1 |
C signedness in SIGNEDSTATIC_EN mode
| Value | F9B0 |
|---|---|
| DISABLED | - |
| ENABLED | 1 |
if ENABLED primitive is reset by user GSR
| Value | F10B0 |
|---|---|
| DISABLED | 0 |
| ENABLED | 1 |
PREADD9_L0 primitive mode
| Value | F10B0 | F16B0 | F18B0 |
|---|---|---|---|
| NONE | 1 | 1 | 1 |
| PREADD9_CORE | - | - | - |
selects 2nd pre-adder operand
| Value | F11B0 |
|---|---|
| INPUT_B_AS_PREADDER_OPERAND | - |
| INPUT_C_AS_PREADDER_OPERAND | 1 |
enable pre-adder carry cascade
| Value | F12B0 |
|---|---|
| DISABLED | - |
| ENABLED | 1 |
register enable or bypass for BL
| Value | F13B0 |
|---|---|
| BYPASS | 1 |
| REGISTER | - |
register enable or bypass for BR0
| Value | F14B0 |
|---|---|
| BYPASS | 1 |
| REGISTER | - |
register enable or bypass for BR1
| Value | F15B0 |
|---|---|
| BYPASS | 1 |
| REGISTER | - |
RSTB gating and inversion control
| Value | F16B0 | F17B0 |
|---|---|---|
| 0 | - | - |
| INV | 1 | 1 |
| RSTB | 1 | - |
RSTCL gating and inversion control
| Value | F18B0 | F19B0 |
|---|---|---|
| 0 | - | - |
| INV | 1 | 1 |
| RSTCL | 1 | - |
use left shift register for B
| Value | F20B0 |
|---|---|
| BYPASS | 1 |
| REGISTER | - |
use right shift register for B
| Value | F21B0 |
|---|---|
| BYPASS | 1 |
| REGISTER | - |
B and C signedness from parameters (ENABLED) or inputs
| Value | F22B0 |
|---|---|
| DISABLED | - |
| ENABLED | 1 |
use 18-bit shift register for B
| Value | F0B0 |
|---|---|
| DISABLED | - |
| ENABLED | 1 |
preadder function
| Value | F23B0 |
|---|---|
| ADDITION | 1 |
| SUBTRACTION | - |
CEP gating and inversion control
| Value | F50B0 | F51B0 |
|---|---|---|
| 1 | 1 | 1 |
| CEP | - | - |
| INV | - | 1 |
clock gating and inversion control
| Value | F52B0 | F53B0 |
|---|---|---|
| 0 | - | - |
| CLK | 1 | - |
| INV | 1 | 1 |
if ENABLED primitive is reset by user GSR
| Value | F54B0 |
|---|---|
| DISABLED | 0 |
| ENABLED | 1 |
REG18_L0_0 primitive mode
| Value | F54B0 | F56B0 |
|---|---|---|
| NONE | 1 | 1 |
| REG18_CORE | - | - |
register enable or bypass
| Value | F55B0 |
|---|---|
| BYPASS | 1 |
| REGISTER | - |
RSTP gating and inversion control
| Value | F56B0 | F57B0 |
|---|---|---|
| 0 | - | - |
| INV | 1 | 1 |
| RSTP | 1 | - |