DOSCL_P18_V18 Tile Documentation

Config Bitmap

 
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Routing Muxes

Mux driving N1:JCLKOUT_I0

Source F9B0 F10B0 F11B0
N1:JPCLK_I0 - - 1
N1:JECLK0_I0 1 - -
N1:JECLK1_I0 1 - 1
N1:JECLK2_I0 1 1 -
N1:JECLK3_I0 1 1 1

Configuration Enums

Configuration enum BANK5.VREF1_USED

use VREF1 input for bank 5

Value F94B1
OFF -
ON 1

Configuration enum DDRDLL.ENA_ROUNDOFF

Value F4B0
DISABLED -
ENABLED 1

Configuration enum DDRDLL.FORCE_MAX_DELAY

Value F5B0
CODE_OR_LOCK_FROM_DLL_LOOP -
FORCE_LOCK_AND_CODE 1

Configuration enum DDRDLL.GSR

DDRDLL GSR mask

Value F1B0
DISABLED 1
ENABLED -

Configuration enum DDRDLL.RSTMUX

Value F6B0
INV -
RST 1

Fixed Connections

SourceSink
N1:JCODE0_DDRDLL_CORE_I1 G:JCODEI00_I_DQS_TOP_DLL_CODE_ROUTING_MUX
N1:JCODE1_DDRDLL_CORE_I1 G:JCODEI01_I_DQS_TOP_DLL_CODE_ROUTING_MUX
N1:JCODE2_DDRDLL_CORE_I1 G:JCODEI02_I_DQS_TOP_DLL_CODE_ROUTING_MUX
N1:JCODE3_DDRDLL_CORE_I1 G:JCODEI03_I_DQS_TOP_DLL_CODE_ROUTING_MUX
N1:JCODE4_DDRDLL_CORE_I1 G:JCODEI04_I_DQS_TOP_DLL_CODE_ROUTING_MUX
N1:JCODE5_DDRDLL_CORE_I1 G:JCODEI05_I_DQS_TOP_DLL_CODE_ROUTING_MUX
N1:JCODE6_DDRDLL_CORE_I1 G:JCODEI06_I_DQS_TOP_DLL_CODE_ROUTING_MUX
N1:JCODE7_DDRDLL_CORE_I1 G:JCODEI07_I_DQS_TOP_DLL_CODE_ROUTING_MUX
N1:JCODE8_DDRDLL_CORE_I1 G:JCODEI08_I_DQS_TOP_DLL_CODE_ROUTING_MUX
N1:JCODE0_DDRDLL_CORE_I1 G:JD0_I4_0
N1:JCODE1_DDRDLL_CORE_I1 G:JD0_I4_1
N1:JCODE2_DDRDLL_CORE_I1 G:JD0_I4_2
N1:JCODE3_DDRDLL_CORE_I1 G:JD0_I4_3
N1:JCODE4_DDRDLL_CORE_I1 G:JD0_I4_4
N1:JCODE5_DDRDLL_CORE_I1 G:JD0_I4_5
N1:JCODE6_DDRDLL_CORE_I1 G:JD0_I4_6
N1:JCODE7_DDRDLL_CORE_I1 G:JD0_I4_7
N1:JCODE8_DDRDLL_CORE_I1 G:JD0_I4_8
N1:JCLKOUT_I0 N1:JCLKIN_DDRDLL_CORE_I1
G:JCLKOUT_ECLKDDRL_0 N1:JECLK0_I0
G:JCLKOUT_ECLKDDRL_1 N1:JECLK1_I0
G:JCLKOUT_ECLKDDRL_2 N1:JECLK2_I0
G:JCLKOUT_ECLKDDRL_3 N1:JECLK3_I0
N1:JDCNTL0_DDRDLL_CORE_I1 N1:JF0
N1:JDCNTL1_DDRDLL_CORE_I1 N1:JF1
N1:JDCNTL2_DDRDLL_CORE_I1 N1:JF2
N1:JDCNTL3_DDRDLL_CORE_I1 N1:JF3
N1:JDCNTL4_DDRDLL_CORE_I1 N1:JF4
N1:JDCNTL5_DDRDLL_CORE_I1 N1:JF5
N1:JDCNTL6_DDRDLL_CORE_I1 N1:JF6
N1:JDCNTL7_DDRDLL_CORE_I1 N1:JF7
N1:JCIBMUXOUTC2 N1:JFREEZE_DDRDLL_CORE_I1
N1:JCLK1 N1:JPCLK_I0
N1:JDCNTL8_DDRDLL_CORE_I1 N1:JQ0
N1:JDIVOSCIB_DDRDLL_CORE_I1 N1:JQ1
N1:JLOCK_DDRDLL_CORE_I1 N1:JQ2
N1:JLSR1 N1:JRST_DDRDLL_CORE_I1
N1:JCIBMUXOUTD1 N1:JUDDCNTL_N_DDRDLL_CORE_I1