|
|
|
|
|
I |
I |
I |
|
|
R |
D |
R |
|
|
G |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| Source | F4B0 | F5B0 | F6B0 |
|---|---|---|---|
| W1:JECLK0_I0 | - | - | 1 |
| W1:JECLK2_I0 | - | 1 | 1 |
| W1:JPCLK_I0 | 1 | - | - |
| W1:JECLK1_I0 | 1 | - | 1 |
| W1:JECLK3_I0 | 1 | 1 | 1 |
| Value | F11B0 |
|---|---|
| DISABLED | - |
| ENABLED | 1 |
| Value | F10B0 |
|---|---|
| CODE_OR_LOCK_FROM_DLL_LOOP | - |
| FORCE_LOCK_AND_CODE | 1 |
DDRDLL GSR mask
| Value | F14B0 |
|---|---|
| DISABLED | 1 |
| ENABLED | - |
| Value | F9B0 |
|---|---|
| INV | - |
| RST | 1 |
| Source | Sink | |
|---|---|---|
| W1:JCODE0_DDRDLL_CORE_I1 | → | G:JCODEI10_I_DQS_TOP_DLL_CODE_ROUTING_MUX |
| W1:JCODE1_DDRDLL_CORE_I1 | → | G:JCODEI11_I_DQS_TOP_DLL_CODE_ROUTING_MUX |
| W1:JCODE2_DDRDLL_CORE_I1 | → | G:JCODEI12_I_DQS_TOP_DLL_CODE_ROUTING_MUX |
| W1:JCODE3_DDRDLL_CORE_I1 | → | G:JCODEI13_I_DQS_TOP_DLL_CODE_ROUTING_MUX |
| W1:JCODE4_DDRDLL_CORE_I1 | → | G:JCODEI14_I_DQS_TOP_DLL_CODE_ROUTING_MUX |
| W1:JCODE5_DDRDLL_CORE_I1 | → | G:JCODEI15_I_DQS_TOP_DLL_CODE_ROUTING_MUX |
| W1:JCODE6_DDRDLL_CORE_I1 | → | G:JCODEI16_I_DQS_TOP_DLL_CODE_ROUTING_MUX |
| W1:JCODE7_DDRDLL_CORE_I1 | → | G:JCODEI17_I_DQS_TOP_DLL_CODE_ROUTING_MUX |
| W1:JCODE8_DDRDLL_CORE_I1 | → | G:JCODEI18_I_DQS_TOP_DLL_CODE_ROUTING_MUX |
| W1:JCODE0_DDRDLL_CORE_I1 | → | G:JD1_I4_0 |
| W1:JCODE1_DDRDLL_CORE_I1 | → | G:JD1_I4_1 |
| W1:JCODE2_DDRDLL_CORE_I1 | → | G:JD1_I4_2 |
| W1:JCODE3_DDRDLL_CORE_I1 | → | G:JD1_I4_3 |
| W1:JCODE4_DDRDLL_CORE_I1 | → | G:JD1_I4_4 |
| W1:JCODE5_DDRDLL_CORE_I1 | → | G:JD1_I4_5 |
| W1:JCODE6_DDRDLL_CORE_I1 | → | G:JD1_I4_6 |
| W1:JCODE7_DDRDLL_CORE_I1 | → | G:JD1_I4_7 |
| W1:JCODE8_DDRDLL_CORE_I1 | → | G:JD1_I4_8 |
| W1:JCLKOUT_I0 | → | W1:JCLKIN_DDRDLL_CORE_I1 |
| G:JCLKOUT_ECLKDDRR_0 | → | W1:JECLK0_I0 |
| G:JCLKOUT_ECLKDDRR_1 | → | W1:JECLK1_I0 |
| G:JCLKOUT_ECLKDDRR_2 | → | W1:JECLK2_I0 |
| G:JCLKOUT_ECLKDDRR_3 | → | W1:JECLK3_I0 |
| W1:JDCNTL0_DDRDLL_CORE_I1 | → | W1:JF0 |
| W1:JDCNTL1_DDRDLL_CORE_I1 | → | W1:JF1 |
| W1:JDCNTL2_DDRDLL_CORE_I1 | → | W1:JF2 |
| W1:JDCNTL3_DDRDLL_CORE_I1 | → | W1:JF3 |
| W1:JDCNTL4_DDRDLL_CORE_I1 | → | W1:JF4 |
| W1:JDCNTL5_DDRDLL_CORE_I1 | → | W1:JF5 |
| W1:JDCNTL6_DDRDLL_CORE_I1 | → | W1:JF6 |
| W1:JDCNTL7_DDRDLL_CORE_I1 | → | W1:JF7 |
| W1:JCIBMUXOUTC2 | → | W1:JFREEZE_DDRDLL_CORE_I1 |
| W1:JCLK1 | → | W1:JPCLK_I0 |
| W1:JDCNTL8_DDRDLL_CORE_I1 | → | W1:JQ0 |
| W1:JDIVOSCIB_DDRDLL_CORE_I1 | → | W1:JQ1 |
| W1:JLOCK_DDRDLL_CORE_I1 | → | W1:JQ2 |
| W1:JLSR1 | → | W1:JRST_DDRDLL_CORE_I1 |
| W1:JCIBMUXOUTD1 | → | W1:JUDDCNTL_N_DDRDLL_CORE_I1 |