CMUX_1 Tile Documentation

Config Bitmap

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Routing Muxes

Mux driving N1W1:JDCSMUXOUT_DCSMUX_CORE_DCSMUX0

Source F3B0 F4B0 F5B0 F7B0 F8B0 F9B0
G:JVPFN0_DCSMUX_CORE_DCSMUX0 0 0 0 0 0 1
G:JVPFS0_DCSMUX_CORE_DCSMUX0 0 0 0 0 1 0
G:JVPFN16_DCSMUX_CORE_DCSMUX0 0 0 0 0 1 1
G:JHPFE4_DCSMUX_CORE_DCSMUX0 0 0 0 1 0 0
G:JVPFN8_DCSMUX_CORE_DCSMUX0 0 0 0 1 0 1
G:JVPFS8_DCSMUX_CORE_DCSMUX0 0 0 0 1 1 0
G:JHPFW6_DCSMUX_CORE_DCSMUX0 0 0 0 1 1 1
G:JHPFE0_DCSMUX_CORE_DCSMUX0 0 0 1 0 0 0
G:JVPFN4_DCSMUX_CORE_DCSMUX0 0 0 1 0 0 1
G:JVPFS4_DCSMUX_CORE_DCSMUX0 0 0 1 0 1 0
G:JHPFW2_DCSMUX_CORE_DCSMUX0 0 0 1 0 1 1
G:JHPFE8_DCSMUX_CORE_DCSMUX0 0 0 1 1 0 0
G:JVPFN12_DCSMUX_CORE_DCSMUX0 0 0 1 1 0 1
G:JVPFS12_DCSMUX_CORE_DCSMUX0 0 0 1 1 1 0
G:JHPFW10_DCSMUX_CORE_DCSMUX0 0 0 1 1 1 1
N1W1:JJCLKUR_DCSMUX_CORE_DCSMUX0 0 1 0 0 0 0
G:JVPFN2_DCSMUX_CORE_DCSMUX0 0 1 0 0 0 1
G:JVPFS2_DCSMUX_CORE_DCSMUX0 0 1 0 0 1 0
G:JHPFW0_DCSMUX_CORE_DCSMUX0 0 1 0 0 1 1
G:JHPFE6_DCSMUX_CORE_DCSMUX0 0 1 0 1 0 0
G:JVPFN10_DCSMUX_CORE_DCSMUX0 0 1 0 1 0 1
G:JVPFS10_DCSMUX_CORE_DCSMUX0 0 1 0 1 1 0
G:JHPFW8_DCSMUX_CORE_DCSMUX0 0 1 0 1 1 1
G:JHPFE2_DCSMUX_CORE_DCSMUX0 0 1 1 0 0 0
G:JVPFN6_DCSMUX_CORE_DCSMUX0 0 1 1 0 0 1
G:JVPFS6_DCSMUX_CORE_DCSMUX0 0 1 1 0 1 0
G:JHPFW4_DCSMUX_CORE_DCSMUX0 0 1 1 0 1 1
G:JHPFE10_DCSMUX_CORE_DCSMUX0 0 1 1 1 0 0
G:JVPFN14_DCSMUX_CORE_DCSMUX0 0 1 1 1 0 1
G:JVPFS14_DCSMUX_CORE_DCSMUX0 0 1 1 1 1 0
N1W1:JJCLKLR_DCSMUX_CORE_DCSMUX0 0 1 1 1 1 1
N1W1:JJCLKLL_DCSMUX_CORE_DCSMUX0 1 0 0 0 0 0
G:JVPFN1_DCSMUX_CORE_DCSMUX0 1 0 0 0 0 1
G:JVPFS1_DCSMUX_CORE_DCSMUX0 1 0 0 0 1 0
G:JVPFN17_DCSMUX_CORE_DCSMUX0 1 0 0 0 1 1
G:JHPFE5_DCSMUX_CORE_DCSMUX0 1 0 0 1 0 0
G:JVPFN9_DCSMUX_CORE_DCSMUX0 1 0 0 1 0 1
G:JVPFS9_DCSMUX_CORE_DCSMUX0 1 0 0 1 1 0
G:JHPFW7_DCSMUX_CORE_DCSMUX0 1 0 0 1 1 1
G:JHPFE1_DCSMUX_CORE_DCSMUX0 1 0 1 0 0 0
G:JVPFN5_DCSMUX_CORE_DCSMUX0 1 0 1 0 0 1
G:JVPFS5_DCSMUX_CORE_DCSMUX0 1 0 1 0 1 0
G:JHPFW3_DCSMUX_CORE_DCSMUX0 1 0 1 0 1 1
G:JHPFE9_DCSMUX_CORE_DCSMUX0 1 0 1 1 0 0
G:JVPFN13_DCSMUX_CORE_DCSMUX0 1 0 1 1 0 1
G:JVPFS13_DCSMUX_CORE_DCSMUX0 1 0 1 1 1 0
G:JHPFW11_DCSMUX_CORE_DCSMUX0 1 0 1 1 1 1
N1W1:JJCLKUL_DCSMUX_CORE_DCSMUX0 1 1 0 0 0 0
G:JVPFN3_DCSMUX_CORE_DCSMUX0 1 1 0 0 0 1
G:JVPFS3_DCSMUX_CORE_DCSMUX0 1 1 0 0 1 0
G:JHPFW1_DCSMUX_CORE_DCSMUX0 1 1 0 0 1 1
G:JHPFE7_DCSMUX_CORE_DCSMUX0 1 1 0 1 0 0
G:JVPFN11_DCSMUX_CORE_DCSMUX0 1 1 0 1 0 1
G:JVPFS11_DCSMUX_CORE_DCSMUX0 1 1 0 1 1 0
G:JHPFW9_DCSMUX_CORE_DCSMUX0 1 1 0 1 1 1
G:JHPFE3_DCSMUX_CORE_DCSMUX0 1 1 1 0 0 0
G:JVPFN7_DCSMUX_CORE_DCSMUX0 1 1 1 0 0 1
G:JVPFS7_DCSMUX_CORE_DCSMUX0 1 1 1 0 1 0
G:JHPFW5_DCSMUX_CORE_DCSMUX0 1 1 1 0 1 1
G:JHPFE11_DCSMUX_CORE_DCSMUX0 1 1 1 1 0 0
G:JVPFN15_DCSMUX_CORE_DCSMUX0 1 1 1 1 0 1
G:JVPFS15_DCSMUX_CORE_DCSMUX0 1 1 1 1 1 0

Mux driving N1W1:JDCSMUXOUT_DCSMUX_CORE_DCSMUX1

Source F10B0 F11B0 F12B0 F14B0 F15B0 F16B0
G:JVPFN0_DCSMUX_CORE_DCSMUX1 0 0 0 0 0 1
G:JVPFS0_DCSMUX_CORE_DCSMUX1 0 0 0 0 1 0
G:JVPFN16_DCSMUX_CORE_DCSMUX1 0 0 0 0 1 1
G:JHPFE4_DCSMUX_CORE_DCSMUX1 0 0 0 1 0 0
G:JVPFN8_DCSMUX_CORE_DCSMUX1 0 0 0 1 0 1
G:JVPFS8_DCSMUX_CORE_DCSMUX1 0 0 0 1 1 0
G:JHPFW6_DCSMUX_CORE_DCSMUX1 0 0 0 1 1 1
G:JHPFE0_DCSMUX_CORE_DCSMUX1 0 0 1 0 0 0
G:JVPFN4_DCSMUX_CORE_DCSMUX1 0 0 1 0 0 1
G:JVPFS4_DCSMUX_CORE_DCSMUX1 0 0 1 0 1 0
G:JHPFW2_DCSMUX_CORE_DCSMUX1 0 0 1 0 1 1
G:JHPFE8_DCSMUX_CORE_DCSMUX1 0 0 1 1 0 0
G:JVPFN12_DCSMUX_CORE_DCSMUX1 0 0 1 1 0 1
G:JVPFS12_DCSMUX_CORE_DCSMUX1 0 0 1 1 1 0
G:JHPFW10_DCSMUX_CORE_DCSMUX1 0 0 1 1 1 1
N1W1:JJCLKUR_DCSMUX_CORE_DCSMUX1 0 1 0 0 0 0
G:JVPFN2_DCSMUX_CORE_DCSMUX1 0 1 0 0 0 1
G:JVPFS2_DCSMUX_CORE_DCSMUX1 0 1 0 0 1 0
G:JHPFW0_DCSMUX_CORE_DCSMUX1 0 1 0 0 1 1
G:JHPFE6_DCSMUX_CORE_DCSMUX1 0 1 0 1 0 0
G:JVPFN10_DCSMUX_CORE_DCSMUX1 0 1 0 1 0 1
G:JVPFS10_DCSMUX_CORE_DCSMUX1 0 1 0 1 1 0
G:JHPFW8_DCSMUX_CORE_DCSMUX1 0 1 0 1 1 1
G:JHPFE2_DCSMUX_CORE_DCSMUX1 0 1 1 0 0 0
G:JVPFN6_DCSMUX_CORE_DCSMUX1 0 1 1 0 0 1
G:JVPFS6_DCSMUX_CORE_DCSMUX1 0 1 1 0 1 0
G:JHPFW4_DCSMUX_CORE_DCSMUX1 0 1 1 0 1 1
G:JHPFE10_DCSMUX_CORE_DCSMUX1 0 1 1 1 0 0
G:JVPFN14_DCSMUX_CORE_DCSMUX1 0 1 1 1 0 1
G:JVPFS14_DCSMUX_CORE_DCSMUX1 0 1 1 1 1 0
N1W1:JJCLKLR_DCSMUX_CORE_DCSMUX1 0 1 1 1 1 1
N1W1:JJCLKLL_DCSMUX_CORE_DCSMUX1 1 0 0 0 0 0
G:JVPFN1_DCSMUX_CORE_DCSMUX1 1 0 0 0 0 1
G:JVPFS1_DCSMUX_CORE_DCSMUX1 1 0 0 0 1 0
G:JVPFN17_DCSMUX_CORE_DCSMUX1 1 0 0 0 1 1
G:JHPFE5_DCSMUX_CORE_DCSMUX1 1 0 0 1 0 0
G:JVPFN9_DCSMUX_CORE_DCSMUX1 1 0 0 1 0 1
G:JVPFS9_DCSMUX_CORE_DCSMUX1 1 0 0 1 1 0
G:JHPFW7_DCSMUX_CORE_DCSMUX1 1 0 0 1 1 1
G:JHPFE1_DCSMUX_CORE_DCSMUX1 1 0 1 0 0 0
G:JVPFN5_DCSMUX_CORE_DCSMUX1 1 0 1 0 0 1
G:JVPFS5_DCSMUX_CORE_DCSMUX1 1 0 1 0 1 0
G:JHPFW3_DCSMUX_CORE_DCSMUX1 1 0 1 0 1 1
G:JHPFE9_DCSMUX_CORE_DCSMUX1 1 0 1 1 0 0
G:JVPFN13_DCSMUX_CORE_DCSMUX1 1 0 1 1 0 1
G:JVPFS13_DCSMUX_CORE_DCSMUX1 1 0 1 1 1 0
G:JHPFW11_DCSMUX_CORE_DCSMUX1 1 0 1 1 1 1
N1W1:JJCLKUL_DCSMUX_CORE_DCSMUX1 1 1 0 0 0 0
G:JVPFN3_DCSMUX_CORE_DCSMUX1 1 1 0 0 0 1
G:JVPFS3_DCSMUX_CORE_DCSMUX1 1 1 0 0 1 0
G:JHPFW1_DCSMUX_CORE_DCSMUX1 1 1 0 0 1 1
G:JHPFE7_DCSMUX_CORE_DCSMUX1 1 1 0 1 0 0
G:JVPFN11_DCSMUX_CORE_DCSMUX1 1 1 0 1 0 1
G:JVPFS11_DCSMUX_CORE_DCSMUX1 1 1 0 1 1 0
G:JHPFW9_DCSMUX_CORE_DCSMUX1 1 1 0 1 1 1
G:JHPFE3_DCSMUX_CORE_DCSMUX1 1 1 1 0 0 0
G:JVPFN7_DCSMUX_CORE_DCSMUX1 1 1 1 0 0 1
G:JVPFS7_DCSMUX_CORE_DCSMUX1 1 1 1 0 1 0
G:JHPFW5_DCSMUX_CORE_DCSMUX1 1 1 1 0 1 1
G:JHPFE11_DCSMUX_CORE_DCSMUX1 1 1 1 1 0 0
G:JVPFN15_DCSMUX_CORE_DCSMUX1 1 1 1 1 0 1
G:JVPFS15_DCSMUX_CORE_DCSMUX1 1 1 1 1 1 0

Mux driving N1W1:JHPRX0_CMUX_CORE_CMUX1

Source F22B0 F23B0 F24B0 F25B0 F26B0
G:JVPFS13_CMUX_CORE_CMUX1 0 0 1 0 1
G:JVPFS3_CMUX_CORE_CMUX1 0 0 1 1 0
G:JHPFW7_CMUX_CORE_CMUX1 0 0 1 1 1
G:JVPFS8_CMUX_CORE_CMUX1 0 1 0 0 1
G:JVPFN16_CMUX_CORE_CMUX1 0 1 0 1 1
G:JVPFN9_CMUX_CORE_CMUX1 0 1 1 0 1
G:JVPFS5_CMUX_CORE_CMUX1 0 1 1 1 0
G:JVPFS6_CMUX_CORE_CMUX1 1 0 0 0 1
G:JVPFN13_CMUX_CORE_CMUX1 1 0 0 1 1
G:JVPFN1_CMUX_CORE_CMUX1 1 0 1 0 1
G:JVPFS4_CMUX_CORE_CMUX1 1 0 1 1 0
N1W1:JJCLKLL_CMUX_CORE_CMUX1 1 0 1 1 1
G:JVPFS10_CMUX_CORE_CMUX1 1 1 0 0 1
G:JVPFS2_CMUX_CORE_CMUX1 1 1 0 1 0
G:JHPFW0_CMUX_CORE_CMUX1 1 1 0 1 1

Mux driving N1W1:JHPRX1_CMUX_CORE_CMUX1

Source F27B0 F28B0 F29B0 F30B0 F31B0
G:JHPFE4_CMUX_CORE_CMUX1 0 0 1 0 1
G:JVPFN2_CMUX_CORE_CMUX1 0 0 1 1 0
G:JHPFW7_CMUX_CORE_CMUX1 0 0 1 1 1
G:JVPFN14_CMUX_CORE_CMUX1 0 1 0 0 1
G:JHPFW3_CMUX_CORE_CMUX1 0 1 0 1 1
G:JHPFE9_CMUX_CORE_CMUX1 0 1 1 0 1
G:JVPFN9_CMUX_CORE_CMUX1 0 1 1 1 0
G:JVPFN11_CMUX_CORE_CMUX1 1 0 0 0 1
G:JHPFE10_CMUX_CORE_CMUX1 1 0 0 1 1
G:JHPFE6_CMUX_CORE_CMUX1 1 0 1 0 1
G:JVPFN7_CMUX_CORE_CMUX1 1 0 1 1 0
G:JHPFW8_CMUX_CORE_CMUX1 1 0 1 1 1
G:JVPFN15_CMUX_CORE_CMUX1 1 1 0 0 1
G:JVPFS14_CMUX_CORE_CMUX1 1 1 0 1 0
G:JHPFW5_CMUX_CORE_CMUX1 1 1 0 1 1

Mux driving N1W1:JHPRX2_CMUX_CORE_CMUX1

Source F32B0 F33B0 F34B0 F35B0 F36B0
G:JHPFE1_CMUX_CORE_CMUX1 0 0 1 0 1
G:JVPFS13_CMUX_CORE_CMUX1 0 0 1 1 0
G:JHPFE10_CMUX_CORE_CMUX1 0 0 1 1 1
G:JVPFN5_CMUX_CORE_CMUX1 0 1 0 0 1
G:JHPFE7_CMUX_CORE_CMUX1 0 1 0 1 1
G:JHPFE4_CMUX_CORE_CMUX1 0 1 1 0 1
G:JVPFN1_CMUX_CORE_CMUX1 0 1 1 1 0
N1W1:JJCLKLR_CMUX_CORE_CMUX1 0 1 1 1 1
G:JVPFN3_CMUX_CORE_CMUX1 1 0 0 0 1
G:JHPFE5_CMUX_CORE_CMUX1 1 0 0 1 1
G:JHPFE3_CMUX_CORE_CMUX1 1 0 1 0 1
G:JVPFN0_CMUX_CORE_CMUX1 1 0 1 1 0
N1W1:JJCLKUR_CMUX_CORE_CMUX1 1 0 1 1 1
G:JVPFN16_CMUX_CORE_CMUX1 1 1 0 0 1
G:JVPFS1_CMUX_CORE_CMUX1 1 1 0 1 0
G:JHPFE9_CMUX_CORE_CMUX1 1 1 0 1 1

Mux driving N1W1:JHPRX3_CMUX_CORE_CMUX1

Source F37B0 F38B0 F39B0 F40B0 F41B0
G:JHPFW1_CMUX_CORE_CMUX1 0 0 1 0 1
G:JVPFS9_CMUX_CORE_CMUX1 0 0 1 1 0
G:JHPFW10_CMUX_CORE_CMUX1 0 0 1 1 1
G:JHPFE5_CMUX_CORE_CMUX1 0 1 0 0 1
G:JHPFW7_CMUX_CORE_CMUX1 0 1 0 1 1
G:JHPFW5_CMUX_CORE_CMUX1 0 1 1 0 1
G:JVPFN10_CMUX_CORE_CMUX1 0 1 1 1 0
N1W1:JJCLKLL_CMUX_CORE_CMUX1 0 1 1 1 1
G:JHPFE3_CMUX_CORE_CMUX1 1 0 0 0 1
G:JHPFW6_CMUX_CORE_CMUX1 1 0 0 1 1
G:JHPFW3_CMUX_CORE_CMUX1 1 0 1 0 1
G:JVPFN0_CMUX_CORE_CMUX1 1 0 1 1 0
G:JHPFW11_CMUX_CORE_CMUX1 1 0 1 1 1
G:JHPFW0_CMUX_CORE_CMUX1 1 1 0 0 1
G:JVPFS3_CMUX_CORE_CMUX1 1 1 0 1 0
G:JHPFW9_CMUX_CORE_CMUX1 1 1 0 1 1

Mux driving N1W1:JHPRX4_CMUX_CORE_CMUX1

Source F42B0 F43B0 F44B0 F45B0 F46B0
G:JVPFN8_CMUX_CORE_CMUX1 0 0 1 0 1
G:JVPFS1_CMUX_CORE_CMUX1 0 0 1 1 0
G:JHPFE11_CMUX_CORE_CMUX1 0 0 1 1 1
G:JVPFN0_CMUX_CORE_CMUX1 0 1 0 0 1
G:JHPFE1_CMUX_CORE_CMUX1 0 1 0 1 1
G:JVPFN17_CMUX_CORE_CMUX1 0 1 1 0 1
G:JVPFS8_CMUX_CORE_CMUX1 0 1 1 1 0
N1W1:JJCLKLL_CMUX_CORE_CMUX1 0 1 1 1 1
G:JVPFS15_CMUX_CORE_CMUX1 1 0 0 0 1
G:JHPFE0_CMUX_CORE_CMUX1 1 0 0 1 1
G:JVPFN12_CMUX_CORE_CMUX1 1 0 1 0 1
G:JVPFS2_CMUX_CORE_CMUX1 1 0 1 1 0
G:JHPFW5_CMUX_CORE_CMUX1 1 0 1 1 1
G:JVPFN2_CMUX_CORE_CMUX1 1 1 0 0 1
G:JVPFS0_CMUX_CORE_CMUX1 1 1 0 1 0
G:JHPFE6_CMUX_CORE_CMUX1 1 1 0 1 1

Mux driving N1W1:JHPRX5_CMUX_CORE_CMUX1

Source F47B0 F48B0 F49B0 F50B0 F51B0
G:JVPFN7_CMUX_CORE_CMUX1 0 0 1 0 1
G:JVPFS2_CMUX_CORE_CMUX1 0 0 1 1 0
G:JHPFW9_CMUX_CORE_CMUX1 0 0 1 1 1
G:JVPFS10_CMUX_CORE_CMUX1 0 1 0 0 1
G:JHPFW1_CMUX_CORE_CMUX1 0 1 0 1 1
G:JHPFE4_CMUX_CORE_CMUX1 0 1 1 0 1
G:JVPFS4_CMUX_CORE_CMUX1 0 1 1 1 0
N1W1:JJCLKUL_CMUX_CORE_CMUX1 0 1 1 1 1
G:JVPFS7_CMUX_CORE_CMUX1 1 0 0 0 1
G:JHPFE8_CMUX_CORE_CMUX1 1 0 0 1 1
G:JHPFE1_CMUX_CORE_CMUX1 1 0 1 0 1
G:JVPFS3_CMUX_CORE_CMUX1 1 0 1 1 0
G:JHPFW10_CMUX_CORE_CMUX1 1 0 1 1 1
G:JVPFN5_CMUX_CORE_CMUX1 1 1 0 0 1
G:JVPFS0_CMUX_CORE_CMUX1 1 1 0 1 0
G:JHPFW8_CMUX_CORE_CMUX1 1 1 0 1 1

Mux driving N1W1:JHPRX6_CMUX_CORE_CMUX1

Source F52B0 F53B0 F54B0 F55B0 F56B0
G:JHPFE2_CMUX_CORE_CMUX1 0 0 1 0 1
G:JVPFS11_CMUX_CORE_CMUX1 0 0 1 1 0
G:JHPFW8_CMUX_CORE_CMUX1 0 0 1 1 1
G:JVPFN11_CMUX_CORE_CMUX1 0 1 0 0 1
G:JHPFW4_CMUX_CORE_CMUX1 0 1 0 1 1
G:JHPFE7_CMUX_CORE_CMUX1 0 1 1 0 1
G:JVPFS13_CMUX_CORE_CMUX1 0 1 1 1 0
G:JHPFW11_CMUX_CORE_CMUX1 0 1 1 1 1
G:JVPFS15_CMUX_CORE_CMUX1 1 0 0 0 1
G:JHPFE8_CMUX_CORE_CMUX1 1 0 0 1 1
G:JHPFE3_CMUX_CORE_CMUX1 1 0 1 0 1
G:JVPFS12_CMUX_CORE_CMUX1 1 0 1 1 0
G:JHPFW10_CMUX_CORE_CMUX1 1 0 1 1 1
G:JVPFN17_CMUX_CORE_CMUX1 1 1 0 0 1
G:JVPFS2_CMUX_CORE_CMUX1 1 1 0 1 0
G:JHPFW7_CMUX_CORE_CMUX1 1 1 0 1 1

Mux driving N1W1:JHPRX7_CMUX_CORE_CMUX1

Source F57B0 F58B0 F59B0 F60B0 F61B0
G:JVPFN13_CMUX_CORE_CMUX1 0 0 1 0 1
G:JVPFS7_CMUX_CORE_CMUX1 0 0 1 1 0
G:JHPFW1_CMUX_CORE_CMUX1 0 0 1 1 1
G:JVPFN6_CMUX_CORE_CMUX1 0 1 0 0 1
G:JHPFE4_CMUX_CORE_CMUX1 0 1 0 1 1
G:JVPFN16_CMUX_CORE_CMUX1 0 1 1 0 1
G:JVPFS14_CMUX_CORE_CMUX1 0 1 1 1 0
N1W1:JDCS0_CMUX_CORE_CMUX1 0 1 1 1 1
G:JVPFS15_CMUX_CORE_CMUX1 1 0 0 0 1
G:JHPFE0_CMUX_CORE_CMUX1 1 0 0 1 1
G:JVPFN15_CMUX_CORE_CMUX1 1 0 1 0 1
G:JVPFS12_CMUX_CORE_CMUX1 1 0 1 1 0
N1W1:JJCLKLL_CMUX_CORE_CMUX1 1 0 1 1 1
G:JVPFN11_CMUX_CORE_CMUX1 1 1 0 0 1
G:JVPFS5_CMUX_CORE_CMUX1 1 1 0 1 0
G:JHPFE5_CMUX_CORE_CMUX1 1 1 0 1 1

Configuration Enums

Configuration enum DCC_C1.DCCEN

DCC bypassed (0) or used as gate (1)

Value F0B0
0 -
1 1

Configuration enum DCC_C2.DCCEN

DCC bypassed (0) or used as gate (1)

Value F1B0
0 -
1 1

Configuration enum DCC_C3.DCCEN

DCC bypassed (0) or used as gate (1)

Value F2B0
0 -
1 1

Configuration enum GSR_CORE.CLKMUX

Value F81B0
CLK -
INV 1

Configuration enum GSR_CORE.GSR

enable global set/reset

Value F80B0
DISABLED -
ENABLED 1

Configuration enum GSR_CORE.GSR_NMUX

Value F83B0
GSR_N -
INV 1

Configuration enum GSR_CORE.GSR_SYNC

synchronise global set/reset

Value F82B0
ASYNC -
SYNC 1