BMID_1_ECLK_2 Tile Documentation

Config Bitmap

 
 
 
 
 
 
 
 
 
 
D
D
D
D
D
D
D
D
D
 
B
B
B
B
 
B
B
B
B
 
B
B
B
B
 
B
B
B
B
 
B
B
B
B
 
B
B
B
B
 
B
B
B
B
 
B
B
B
B
 
B
B
B
B
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
E
 
E
E
E
E
E
E
E
E
E
E
 
 
E
E
E
E
E
E
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
D
 
D
D
D
D
D
D
 
 
D
D
 
 
D
D
D
D
 
 
D
D
 
 
G
G
G
G
 
 
G
G
D
 
E
E
E
E
 
 
E
E
 
 
E
E
E
E
 
 
D
D
 
 
D
D
 
 
D
D
D
 
 
D
 
 
 
 
 
 
 

Routing Muxes

Mux driving G:JECLKOUT0_ECLKCASMUX_CORE_ECLKCASMUX3

Source F93B0 F94B0
N1:JECLKCAS0M0_ECLKCASMUX_CORE_ECLKCASMUX3 - 1
N1:JECLKCAS1M0_ECLKCASMUX_CORE_ECLKCASMUX3 1 -
N1:JECLKSYNCM0_ECLKCASMUX_CORE_ECLKCASMUX3 1 1

Mux driving G:JECLKOUT1_ECLKCASMUX_CORE_ECLKCASMUX3

Source F101B0
N1:JECLKCAS0M1_ECLKCASMUX_CORE_ECLKCASMUX3 -
N1:JECLKCAS1M1_ECLKCASMUX_CORE_ECLKCASMUX3 1
N1:JECLKSYNCM1_ECLKCASMUX_CORE_ECLKCASMUX3 1

Mux driving G:JECLKOUT3_ECLKCASMUX_CORE_ECLKCASMUX4

Source F102B0 F103B0
N1W1:JECLKCAS0M3_ECLKCASMUX_CORE_ECLKCASMUX4 - 1
N1W1:JECLKCAS1M3_ECLKCASMUX_CORE_ECLKCASMUX4 1 -
N1W1:JECLKSYNCM3_ECLKCASMUX_CORE_ECLKCASMUX4 1 1

Mux driving G:JMUXIN0_ECLKBANK_CORE_ECLKBANK3

Source F89B0 F90B0 F91B0 F92B0
G:JPCLKT1_ECLKBANK_CORE_ECLKBANK3 - 1 - -
G:JLRCLKOS4_ECLKBANK_CORE_ECLKBANK3 - 1 - 1
G:JPCLKT0_ECLKBANK_CORE_ECLKBANK3 - 1 1 -
G:JLRCLKOS2_ECLKBANK_CORE_ECLKBANK3 - 1 1 1
G:JPCLKT3_ECLKBANK_CORE_ECLKBANK3 1 - - 1
N1:JECLKCIB0_ECLKBANK_CORE_ECLKBANK3 1 - 1 -
G:JPCLKT2_ECLKBANK_CORE_ECLKBANK3 1 - 1 1
G:JLRCLKOS_ECLKBANK_CORE_ECLKBANK3 1 1 - -
G:JLLCLKOS3_ECLKBANK_CORE_ECLKBANK3 1 1 - 1
G:JLLCLKOS5_ECLKBANK_CORE_ECLKBANK3 1 1 1 -
G:JLLCLKOP_ECLKBANK_CORE_ECLKBANK3 1 1 1 1

Mux driving G:JMUXIN1_ECLKBANK_CORE_ECLKBANK3

Source F95B0 F98B0 F99B0 F100B0
G:JPCLKT1_ECLKBANK_CORE_ECLKBANK3 - 1 - -
G:JLRCLKOS5_ECLKBANK_CORE_ECLKBANK3 - 1 - 1
G:JPCLKT0_ECLKBANK_CORE_ECLKBANK3 - 1 1 -
G:JLRCLKOS3_ECLKBANK_CORE_ECLKBANK3 - 1 1 1
G:JPCLKT3_ECLKBANK_CORE_ECLKBANK3 1 - - 1
N1:JECLKCIB1_ECLKBANK_CORE_ECLKBANK3 1 - 1 -
G:JPCLKT2_ECLKBANK_CORE_ECLKBANK3 1 - 1 1
G:JLRCLKOS2_ECLKBANK_CORE_ECLKBANK3 1 1 - -
G:JLLCLKOS_ECLKBANK_CORE_ECLKBANK3 1 1 - 1
G:JLLCLKOS4_ECLKBANK_CORE_ECLKBANK3 1 1 1 -
G:JLLCLKOP_ECLKBANK_CORE_ECLKBANK3 1 1 1 1

Mux driving G:JMUXIN2_ECLKBANK_CORE_ECLKBANK4

Source F84B0 F86B0 F87B0 F88B0
G:JPCLKT1_ECLKBANK_CORE_ECLKBANK4 - 1 - -
G:JLRCLKOS4_ECLKBANK_CORE_ECLKBANK4 - 1 - 1
G:JPCLKT0_ECLKBANK_CORE_ECLKBANK4 - 1 1 -
G:JLRCLKOS3_ECLKBANK_CORE_ECLKBANK4 - 1 1 1
G:JPCLKT3_ECLKBANK_CORE_ECLKBANK4 1 - - 1
N1W1:JECLKCIB2_ECLKBANK_CORE_ECLKBANK4 1 - 1 -
G:JPCLKT2_ECLKBANK_CORE_ECLKBANK4 1 - 1 1
G:JLRCLKOP_ECLKBANK_CORE_ECLKBANK4 1 1 - -
G:JLLCLKOS2_ECLKBANK_CORE_ECLKBANK4 1 1 - 1
G:JLLCLKOS5_ECLKBANK_CORE_ECLKBANK4 1 1 1 -
G:JLLCLKOS_ECLKBANK_CORE_ECLKBANK4 1 1 1 1

Mux driving G:JVPFN10_BMID_CORE_BMIDMUX

Source F25B0 F26B0 F27B0 F28B0
G:JECLKDIV9_BMID_CORE_BMIDMUX 0 1 0 0
G:JECLKDIV1_BMID_CORE_BMIDMUX 0 1 0 1
G:JECLKDIV5_BMID_CORE_BMIDMUX 0 1 1 0
G:JLRCLKOS3_BMID_CORE_BMIDMUX 0 1 1 1
G:JPCLKCIBB4_BMID_CORE_BMIDMUX 1 0 0 1
G:JPCLKCIBB3_BMID_CORE_BMIDMUX 1 0 1 1
G:JLRCLKOP_BMID_CORE_BMIDMUX 1 1 0 0
G:JPCLKT52_BMID_CORE_BMIDMUX 1 1 0 1
G:JLLCLKOS_BMID_CORE_BMIDMUX 1 1 1 0
G:JPCLKT42_BMID_CORE_BMIDMUX 1 1 1 1

Mux driving G:JVPFN11_BMID_CORE_BMIDMUX

Source F30B0 F31B0 F32B0 F33B0
G:JECLKDIV6_BMID_CORE_BMIDMUX 0 1 0 0
G:JLRCLKOS5_BMID_CORE_BMIDMUX 0 1 0 1
G:JECLKDIV4_BMID_CORE_BMIDMUX 0 1 1 0
G:JLRCLKOS_BMID_CORE_BMIDMUX 0 1 1 1
G:JPCLKCIBB5_BMID_CORE_BMIDMUX 1 0 0 1
G:JPCLKCIBB0_BMID_CORE_BMIDMUX 1 0 1 1
G:JLLCLKOP_BMID_CORE_BMIDMUX 1 1 0 0
G:JPCLKT50_BMID_CORE_BMIDMUX 1 1 0 1
G:JPCLKT53_BMID_CORE_BMIDMUX 1 1 1 0
G:JPCLKT32_BMID_CORE_BMIDMUX 1 1 1 1

Mux driving G:JVPFN12_BMID_CORE_BMIDMUX

Source F35B0 F36B0 F37B0 F38B0
G:JECLKDIV11_BMID_CORE_BMIDMUX 0 1 0 0
G:JECLKDIV2_BMID_CORE_BMIDMUX 0 1 0 1
G:JECLKDIV8_BMID_CORE_BMIDMUX 0 1 1 0
G:JLLCLKOS5_BMID_CORE_BMIDMUX 0 1 1 1
G:JPCLKCIBB5_BMID_CORE_BMIDMUX 1 0 1 1
G:JLLCLKOS2_BMID_CORE_BMIDMUX 1 1 0 0
G:JPCLKT33_BMID_CORE_BMIDMUX 1 1 0 1
G:JPCLKT50_BMID_CORE_BMIDMUX 1 1 1 0
G:JPCLKT30_BMID_CORE_BMIDMUX 1 1 1 1

Mux driving G:JVPFN13_BMID_CORE_BMIDMUX

Source F40B0 F41B0 F42B0 F43B0
G:JPCLKCIBB2_BMID_CORE_BMIDMUX 0 1 0 0
G:JECLKDIV3_BMID_CORE_BMIDMUX 0 1 0 1
G:JECLKDIV8_BMID_CORE_BMIDMUX 0 1 1 0
G:JECLKDIV0_BMID_CORE_BMIDMUX 0 1 1 1
G:JPCLKCIBB4_BMID_CORE_BMIDMUX 1 0 1 1
G:JLLCLKOS3_BMID_CORE_BMIDMUX 1 1 0 0
G:JPCLKT40_BMID_CORE_BMIDMUX 1 1 0 1
G:JPCLKT53_BMID_CORE_BMIDMUX 1 1 1 0
G:JPCLKT31_BMID_CORE_BMIDMUX 1 1 1 1

Mux driving G:JVPFN14_BMID_CORE_BMIDMUX

Source F45B0 F46B0 F47B0 F48B0
G:JECLKDIV9_BMID_CORE_BMIDMUX 0 1 0 0
G:JECLKDIV1_BMID_CORE_BMIDMUX 0 1 0 1
G:JECLKDIV4_BMID_CORE_BMIDMUX 0 1 1 0
G:JLLCLKOS5_BMID_CORE_BMIDMUX 0 1 1 1
G:JPCLKCIBB1_BMID_CORE_BMIDMUX 1 0 1 1
G:JLLCLKOS3_BMID_CORE_BMIDMUX 1 1 0 0
G:JPCLKT43_BMID_CORE_BMIDMUX 1 1 0 1
G:JPCLKT53_BMID_CORE_BMIDMUX 1 1 1 0
G:JPCLKT32_BMID_CORE_BMIDMUX 1 1 1 1

Mux driving G:JVPFN15_BMID_CORE_BMIDMUX

Source F50B0 F51B0 F52B0 F53B0
G:JECLKDIV2_BMID_CORE_BMIDMUX 0 1 0 0
G:JLRCLKOS2_BMID_CORE_BMIDMUX 0 1 0 1
G:JLRCLKOS4_BMID_CORE_BMIDMUX 0 1 1 0
G:JLLCLKOS4_BMID_CORE_BMIDMUX 0 1 1 1
G:JECLKDIV11_BMID_CORE_BMIDMUX 1 0 0 1
G:JECLKDIV7_BMID_CORE_BMIDMUX 1 0 1 1
G:JLLCLKOS2_BMID_CORE_BMIDMUX 1 1 0 0
G:JPCLKT42_BMID_CORE_BMIDMUX 1 1 0 1
G:JPCLKT52_BMID_CORE_BMIDMUX 1 1 1 0
G:JPCLKT30_BMID_CORE_BMIDMUX 1 1 1 1

Mux driving G:JVPFN16_BMID_CORE_BMIDMUX

Source F55B0 F56B0 F57B0 F58B0
G:JPCLKCIBB0_BMID_CORE_BMIDMUX 0 1 0 0
G:JECLKDIV4_BMID_CORE_BMIDMUX 0 1 0 1
G:JECLKDIV7_BMID_CORE_BMIDMUX 0 1 1 0
G:JLRCLKOS3_BMID_CORE_BMIDMUX 0 1 1 1
G:JPCLKCIBB4_BMID_CORE_BMIDMUX 1 0 0 1
G:JPCLKCIBB2_BMID_CORE_BMIDMUX 1 0 1 1
G:JLRCLKOS_BMID_CORE_BMIDMUX 1 1 0 0
G:JPCLKT43_BMID_CORE_BMIDMUX 1 1 0 1
G:JLLCLKOS_BMID_CORE_BMIDMUX 1 1 1 0
G:JPCLKT40_BMID_CORE_BMIDMUX 1 1 1 1

Mux driving G:JVPFN17_BMID_CORE_BMIDMUX

Source F60B0 F61B0 F62B0 F63B0
G:JECLKDIV5_BMID_CORE_BMIDMUX 0 1 0 0
G:JLRCLKOS5_BMID_CORE_BMIDMUX 0 1 0 1
G:JECLKDIV0_BMID_CORE_BMIDMUX 0 1 1 0
G:JLRCLKOP_BMID_CORE_BMIDMUX 0 1 1 1
G:JPCLKCIBB3_BMID_CORE_BMIDMUX 1 0 0 1
G:JECLKDIV10_BMID_CORE_BMIDMUX 1 0 1 1
G:JLLCLKOS4_BMID_CORE_BMIDMUX 1 1 0 0
G:JPCLKT41_BMID_CORE_BMIDMUX 1 1 0 1
G:JPCLKT51_BMID_CORE_BMIDMUX 1 1 1 0
G:JPCLKT31_BMID_CORE_BMIDMUX 1 1 1 1

Mux driving G:JVPFN9_BMID_CORE_BMIDMUX

Source F20B0 F21B0 F22B0 F23B0
G:JPCLKCIBB1_BMID_CORE_BMIDMUX 0 1 0 0
G:JECLKDIV3_BMID_CORE_BMIDMUX 0 1 0 1
G:JECLKDIV8_BMID_CORE_BMIDMUX 0 1 1 0
G:JLRCLKOS4_BMID_CORE_BMIDMUX 0 1 1 1
G:JPCLKCIBB5_BMID_CORE_BMIDMUX 1 0 0 1
G:JPCLKCIBB3_BMID_CORE_BMIDMUX 1 0 1 1
G:JLRCLKOS2_BMID_CORE_BMIDMUX 1 1 0 0
G:JPCLKT51_BMID_CORE_BMIDMUX 1 1 0 1
G:JLLCLKOS4_BMID_CORE_BMIDMUX 1 1 1 0
G:JPCLKT41_BMID_CORE_BMIDMUX 1 1 1 1

Mux driving N1E1:JECLKOUT_ECLKLOGICMUXPLLFB_CORE_ECLKPLLFBR

Source F79B1 F80B1 F81B1 F82B1
G:JLRCLKOS5_ECLKLOGICMUXPLLFB_CORE_ECLKPLLFBR - 1 - -
G:JLRCLKOS3_ECLKLOGICMUXPLLFB_CORE_ECLKPLLFBR - 1 - 1
G:JLRCLKOS4_ECLKLOGICMUXPLLFB_CORE_ECLKPLLFBR - 1 1 -
G:JLRCLKOS2_ECLKLOGICMUXPLLFB_CORE_ECLKPLLFBR - 1 1 1
G:JLRCLKOS_ECLKLOGICMUXPLLFB_CORE_ECLKPLLFBR 1 - - -
G:JLLCLKOS5_ECLKLOGICMUXPLLFB_CORE_ECLKPLLFBR 1 - - 1
G:JLRCLKOP_ECLKLOGICMUXPLLFB_CORE_ECLKPLLFBR 1 - 1 -
G:JLLCLKOS4_ECLKLOGICMUXPLLFB_CORE_ECLKPLLFBR 1 - 1 1
G:JLLCLKOS3_ECLKLOGICMUXPLLFB_CORE_ECLKPLLFBR 1 1 - -
G:JLLCLKOS_ECLKLOGICMUXPLLFB_CORE_ECLKPLLFBR 1 1 - 1
G:JLLCLKOS2_ECLKLOGICMUXPLLFB_CORE_ECLKPLLFBR 1 1 1 -
G:JLLCLKOP_ECLKLOGICMUXPLLFB_CORE_ECLKPLLFBR 1 1 1 1

Configuration Enums

Configuration enum DCC_B10.DCCEN

DCC bypassed (0) or used as gate (1)

Value F11B0
0 -
1 1

Configuration enum DCC_B11.DCCEN

DCC bypassed (0) or used as gate (1)

Value F12B0
0 -
1 1

Configuration enum DCC_B12.DCCEN

DCC bypassed (0) or used as gate (1)

Value F13B0
0 -
1 1

Configuration enum DCC_B13.DCCEN

DCC bypassed (0) or used as gate (1)

Value F14B0
0 -
1 1

Configuration enum DCC_B14.DCCEN

DCC bypassed (0) or used as gate (1)

Value F15B0
0 -
1 1

Configuration enum DCC_B15.DCCEN

DCC bypassed (0) or used as gate (1)

Value F16B0
0 -
1 1

Configuration enum DCC_B16.DCCEN

DCC bypassed (0) or used as gate (1)

Value F17B0
0 -
1 1

Configuration enum DCC_B17.DCCEN

DCC bypassed (0) or used as gate (1)

Value F18B0
0 -
1 1

Configuration enum DCC_B9.DCCEN

DCC bypassed (0) or used as gate (1)

Value F10B0
0 -
1 1

Configuration enum ECLKDIV3A.ECLK_DIV

ECLKDIV divide value

Value F37B1 F67B1 F85B1 F93B1
2 - - 1 -
3P5 - - - 1
4 1 - - -
5 - 1 - -
DISABLE - - - -

Configuration enum ECLKDIV3A.GSR

ECLKDIV GSR mask

Value F59B1
DISABLED 1
ENABLED -

Configuration enum ECLKDIV3B.ECLK_DIV

ECLKDIV divide value

Value F35B1 F38B1 F86B1 F94B1
2 - - 1 -
3P5 - - - 1
4 - 1 - -
5 1 - - -
DISABLE - - - -

Configuration enum ECLKDIV3B.GSR

ECLKDIV GSR mask

Value F60B1
DISABLED 1
ENABLED -

Configuration enum ECLKDIV3C.ECLK_DIV

ECLKDIV divide value

Value F41B1 F51B1 F89B1 F95B1
2 - - 1 -
3P5 - - - 1
4 1 - - -
5 - 1 - -
DISABLE - - - -

Configuration enum ECLKDIV3C.GSR

ECLKDIV GSR mask

Value F61B1
DISABLED 1
ENABLED -

Configuration enum ECLKDIV3D.ECLK_DIV

ECLKDIV divide value

Value F42B1 F52B1 F90B1 F98B1
2 - - 1 -
3P5 - - - 1
4 1 - - -
5 - 1 - -
DISABLE - - - -

Configuration enum ECLKDIV3D.GSR

ECLKDIV GSR mask

Value F62B1
DISABLED 1
ENABLED -

Configuration enum ECLKDIV4A.ECLK_DIV

ECLKDIV divide value

Value F45B1 F55B1
2 - -
3P5 - -
4 1 -
5 - 1
DISABLE - -

Configuration enum ECLKDIV4A.GSR

ECLKDIV GSR mask

Value F65B1
DISABLED 1
ENABLED -

Configuration enum ECLKDIV4B.ECLK_DIV

ECLKDIV divide value

Value F46B1 F56B1
2 - -
3P5 - -
4 1 -
5 - 1
DISABLE - -

Configuration enum ECLKDIV4B.GSR

ECLKDIV GSR mask

Value F66B1
DISABLED 1
ENABLED -

Configuration enum ECLKDIV4C.ECLK_DIV

ECLKDIV divide value

Value F39B1 F49B1
2 - -
3P5 - -
4 1 -
5 - 1
DISABLE - -

Configuration enum ECLKDIV4D.ECLK_DIV

ECLKDIV divide value

Value F40B1 F50B1
2 - -
3P5 - -
4 1 -
5 - 1
DISABLE - -

Configuration enum ECLKSYNC3A.STOP_EN

ECLKSYNC stop control enable

Value F76B1
DISABLE -
ENABLE 1

Configuration enum ECLKSYNC3B.STOP_EN

ECLKSYNC stop control enable

Value F75B1
DISABLE -
ENABLE 1

Configuration enum ECLKSYNC3C.STOP_EN

ECLKSYNC stop control enable

Value F71B1
DISABLE -
ENABLE 1

Configuration enum ECLKSYNC3D.STOP_EN

ECLKSYNC stop control enable

Value F69B1
DISABLE -
ENABLE 1

Configuration enum ECLKSYNC4B.STOP_EN

ECLKSYNC stop control enable

Value F72B1
DISABLE -
ENABLE 1

Configuration enum ECLKSYNC4D.STOP_EN

ECLKSYNC stop control enable

Value F70B1
DISABLE -
ENABLE 1

Fixed Connections

SourceSink
N1:JDIVOUT_ECLKDIV_CORE_ECLKDIVB3_0→ G:JECLKDIV0_BMID_CORE_BMIDMUX
N1:JDIVOUT_ECLKDIV_CORE_ECLKDIVB3_1→ G:JECLKDIV1_BMID_CORE_BMIDMUX
N1:JDIVOUT_ECLKDIV_CORE_ECLKDIVB3_2→ G:JECLKDIV2_BMID_CORE_BMIDMUX
N1:JDIVOUT_ECLKDIV_CORE_ECLKDIVB3_3→ G:JECLKDIV3_BMID_CORE_BMIDMUX
N1E4:JCLKOUT_DLLDEL_CORE_I0→ G:JPCLKT0_ECLKBANK_CORE_ECLKBANK3
N1E5:JCLKOUT_DLLDEL_CORE_I0→ G:JPCLKT2_ECLKBANK_CORE_ECLKBANK3
N1E3:JLSR0→ N1:JDIVRST_ECLKDIV_CORE_ECLKDIVB3_0
N1E3:JLSR1→ N1:JDIVRST_ECLKDIV_CORE_ECLKDIVB3_1
N1E2:JLSR0→ N1:JDIVRST_ECLKDIV_CORE_ECLKDIVB3_2
N1E2:JLSR1→ N1:JDIVRST_ECLKDIV_CORE_ECLKDIVB3_3
N1W2:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC5_0→ N1:JECLKCAS0M0_ECLKCASMUX_CORE_ECLKCASMUX3
N1W2:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC5_1→ N1:JECLKCAS0M1_ECLKCASMUX_CORE_ECLKCASMUX3
N1W2:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC5_2→ N1:JECLKCAS0M2_ECLKCASMUX_CORE_ECLKCASMUX3
N1W2:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC5_3→ N1:JECLKCAS0M3_ECLKCASMUX_CORE_ECLKCASMUX3
N1W1:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC4_0→ N1:JECLKCAS1M0_ECLKCASMUX_CORE_ECLKCASMUX3
N1W1:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC4_1→ N1:JECLKCAS1M1_ECLKCASMUX_CORE_ECLKCASMUX3
N1W1:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC4_2→ N1:JECLKCAS1M2_ECLKCASMUX_CORE_ECLKCASMUX3
N1W1:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC4_3→ N1:JECLKCAS1M3_ECLKCASMUX_CORE_ECLKCASMUX3
N1W1:JCIBMUXOUTB0→ N1:JECLKCIB0_ECLKBANK_CORE_ECLKBANK3
N1W1:JCIBMUXOUTB1→ N1:JECLKCIB1_ECLKBANK_CORE_ECLKBANK3
N1W1:JCIBMUXOUTB2→ N1:JECLKCIB2_ECLKBANK_CORE_ECLKBANK3
N1W1:JCIBMUXOUTB3→ N1:JECLKCIB3_ECLKBANK_CORE_ECLKBANK3
G:JECLKOUT0_ECLKCASMUX_CORE_ECLKCASMUX3→ N1:JECLKIN_ECLKDIV_CORE_ECLKDIVB3_0
G:JECLKOUT1_ECLKCASMUX_CORE_ECLKCASMUX3→ N1:JECLKIN_ECLKDIV_CORE_ECLKDIVB3_1
G:JECLKOUT2_ECLKCASMUX_CORE_ECLKCASMUX3→ N1:JECLKIN_ECLKDIV_CORE_ECLKDIVB3_2
G:JECLKOUT3_ECLKCASMUX_CORE_ECLKCASMUX3→ N1:JECLKIN_ECLKDIV_CORE_ECLKDIVB3_3
G:JMUXIN0_ECLKBANK_CORE_ECLKBANK3→ N1:JECLKIN_ECLKSYNC_CORE_ECLKSYNC3_0
G:JMUXIN1_ECLKBANK_CORE_ECLKBANK3→ N1:JECLKIN_ECLKSYNC_CORE_ECLKSYNC3_1
G:JMUXIN2_ECLKBANK_CORE_ECLKBANK3→ N1:JECLKIN_ECLKSYNC_CORE_ECLKSYNC3_2
G:JMUXIN3_ECLKBANK_CORE_ECLKBANK3→ N1:JECLKIN_ECLKSYNC_CORE_ECLKSYNC3_3
N1:JECLKIN_ECLKSYNC_CORE_ECLKSYNC3_0→ N1:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC3_0
N1:JECLKIN_ECLKSYNC_CORE_ECLKSYNC3_1→ N1:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC3_1
N1:JECLKIN_ECLKSYNC_CORE_ECLKSYNC3_2→ N1:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC3_2
N1:JECLKIN_ECLKSYNC_CORE_ECLKSYNC3_3→ N1:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC3_3
N1:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC3_0→ N1:JECLKSYNCM0_ECLKCASMUX_CORE_ECLKCASMUX3
N1:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC3_1→ N1:JECLKSYNCM1_ECLKCASMUX_CORE_ECLKCASMUX3
N1:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC3_2→ N1:JECLKSYNCM2_ECLKCASMUX_CORE_ECLKCASMUX3
N1:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC3_3→ N1:JECLKSYNCM3_ECLKCASMUX_CORE_ECLKCASMUX3
G:JECLKOUT0_ECLKCASMUX_CORE_ECLKCASMUX3→ N1:JECLKTREE0_ECLKDDRR_0
G:JECLKOUT1_ECLKCASMUX_CORE_ECLKCASMUX3→ N1:JECLKTREE0_ECLKDDRR_1
G:JECLKOUT2_ECLKCASMUX_CORE_ECLKCASMUX3→ N1:JECLKTREE0_ECLKDDRR_2
G:JECLKOUT3_ECLKCASMUX_CORE_ECLKCASMUX3→ N1:JECLKTREE0_ECLKDDRR_3
G:JECLKOUT0_ECLKCASMUX_CORE_ECLKCASMUX4→ N1:JECLKTREE1_ECLKDDRR_0
G:JECLKOUT1_ECLKCASMUX_CORE_ECLKCASMUX4→ N1:JECLKTREE1_ECLKDDRR_1
G:JECLKOUT2_ECLKCASMUX_CORE_ECLKCASMUX4→ N1:JECLKTREE1_ECLKDDRR_2
G:JECLKOUT3_ECLKCASMUX_CORE_ECLKCASMUX4→ N1:JECLKTREE1_ECLKDDRR_3
N1E1:JCIBMUXOUTC2→ N1:JSLIP_ECLKDIV_CORE_ECLKDIVB3_0
N1E1:JCIBMUXOUTC3→ N1:JSLIP_ECLKDIV_CORE_ECLKDIVB3_1
N1E1:JCIBMUXOUTC4→ N1:JSLIP_ECLKDIV_CORE_ECLKDIVB3_2
N1E1:JCIBMUXOUTC5→ N1:JSLIP_ECLKDIV_CORE_ECLKDIVB3_3
N1:JCIBMUXOUTD2→ N1:JSTOP_ECLKSYNC_CORE_ECLKSYNC3_0
N1:JCIBMUXOUTB4→ N1:JSTOP_ECLKSYNC_CORE_ECLKSYNC3_1
N1:JCIBMUXOUTB7→ N1:JSTOP_ECLKSYNC_CORE_ECLKSYNC3_2
N1:JCIBMUXOUTB5→ N1:JSTOP_ECLKSYNC_CORE_ECLKSYNC3_3
N1W2:JCIBMUXOUTA0→ N1:JTESTINP0_ECLKBANK_CORE_ECLKBANK3
N1W2:JCIBMUXOUTA4→ N1:JTESTINP0_ECLKCASMUX_CORE_ECLKCASMUX3
N1W2:JCIBMUXOUTC2→ N1:JTESTINP0_ECLKDIV_CORE_ECLKDIVB3_0
N1W2:JCIBMUXOUTC2→ N1:JTESTINP0_ECLKDIV_CORE_ECLKDIVB3_1
N1W2:JCIBMUXOUTC2→ N1:JTESTINP0_ECLKDIV_CORE_ECLKDIVB3_2
N1W2:JCIBMUXOUTC2→ N1:JTESTINP0_ECLKDIV_CORE_ECLKDIVB3_3
N1W2:JCIBMUXOUTA1→ N1:JTESTINP1_ECLKBANK_CORE_ECLKBANK3
N1W2:JCIBMUXOUTA5→ N1:JTESTINP1_ECLKCASMUX_CORE_ECLKCASMUX3
N1W2:JCIBMUXOUTC3→ N1:JTESTINP1_ECLKDIV_CORE_ECLKDIVB3_0
N1W2:JCIBMUXOUTC3→ N1:JTESTINP1_ECLKDIV_CORE_ECLKDIVB3_1
N1W2:JCIBMUXOUTC3→ N1:JTESTINP1_ECLKDIV_CORE_ECLKDIVB3_2
N1W2:JCIBMUXOUTC3→ N1:JTESTINP1_ECLKDIV_CORE_ECLKDIVB3_3
N1W2:JCIBMUXOUTA2→ N1:JTESTINP2_ECLKBANK_CORE_ECLKBANK3
N1W2:JCIBMUXOUTC4→ N1:JTESTINP2_ECLKDIV_CORE_ECLKDIVB3_0
N1W2:JCIBMUXOUTC4→ N1:JTESTINP2_ECLKDIV_CORE_ECLKDIVB3_1
N1W2:JCIBMUXOUTC4→ N1:JTESTINP2_ECLKDIV_CORE_ECLKDIVB3_2
N1W2:JCIBMUXOUTC4→ N1:JTESTINP2_ECLKDIV_CORE_ECLKDIVB3_3
N1W2:JCIBMUXOUTA3→ N1:JTESTINP3_ECLKBANK_CORE_ECLKBANK3
N1W2:JCIBMUXOUTC5→ N1:JTESTINP3_ECLKDIV_CORE_ECLKDIVB3_0
N1W2:JCIBMUXOUTC5→ N1:JTESTINP3_ECLKDIV_CORE_ECLKDIVB3_1
N1W2:JCIBMUXOUTC5→ N1:JTESTINP3_ECLKDIV_CORE_ECLKDIVB3_2
N1W2:JCIBMUXOUTC5→ N1:JTESTINP3_ECLKDIV_CORE_ECLKDIVB3_3
N1:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC3_0→ N1W1:JECLKCAS0M0_ECLKCASMUX_CORE_ECLKCASMUX4
N1:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC3_1→ N1W1:JECLKCAS0M1_ECLKCASMUX_CORE_ECLKCASMUX4
N1:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC3_2→ N1W1:JECLKCAS0M2_ECLKCASMUX_CORE_ECLKCASMUX4
N1:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC3_3→ N1W1:JECLKCAS0M3_ECLKCASMUX_CORE_ECLKCASMUX4
N1:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC3_0→ N1W2:JECLKCAS1M0_ECLKCASMUX_CORE_ECLKCASMUX5
N1:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC3_1→ N1W2:JECLKCAS1M1_ECLKCASMUX_CORE_ECLKCASMUX5
N1:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC3_2→ N1W2:JECLKCAS1M2_ECLKCASMUX_CORE_ECLKCASMUX5
N1:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC3_3→ N1W2:JECLKCAS1M3_ECLKCASMUX_CORE_ECLKCASMUX5