| Name | Type |
|---|---|
| DCC_B0 | DCC |
| DCC_B1 | DCC |
| DCC_B2 | DCC |
| DCC_B3 | DCC |
| DCC_B4 | DCC |
| DCC_B5 | DCC |
| DCC_B6 | DCC |
| DCC_B7 | DCC |
| DCC_B8 | DCC |
| DCC_B9 | DCC |
| DCC_B10 | DCC |
| DCC_B11 | DCC |
| DCC_B12 | DCC |
| DCC_B13 | DCC |
| DCC_B14 | DCC |
| DCC_B15 | DCC |
| DCC_B16 | DCC |
| DCC_B17 | DCC |
| ECLKSYNC4A | ECLKSYNC_CORE |
| ECLKSYNC4B | ECLKSYNC_CORE |
| ECLKSYNC4C | ECLKSYNC_CORE |
| ECLKSYNC4D | ECLKSYNC_CORE |
| ECLKDIV4A | ECLKDIV_CORE |
| ECLKDIV4B | ECLKDIV_CORE |
| ECLKDIV4C | ECLKDIV_CORE |
| ECLKDIV4D | ECLKDIV_CORE |
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D |
D |
D |
D |
D |
D |
D |
D |
D |
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B |
B |
B |
B |
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B |
B |
B |
B |
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B |
B |
B |
B |
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B |
B |
B |
B |
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B |
B |
B |
B |
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B |
B |
B |
B |
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B |
B |
B |
B |
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B |
B |
B |
B |
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B |
B |
B |
B |
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E |
E |
E |
E |
E |
E |
E |
E |
E |
E |
E |
E |
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E |
D |
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D |
D |
D |
D |
D |
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E |
E |
E |
E |
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E |
E |
E |
E |
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D |
D |
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D |
D |
D |
D |
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D |
D |
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D |
D |
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D |
D |
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G |
G |
G |
G |
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G |
G |
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E |
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E |
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E |
E |
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E |
E |
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D |
D |
D |
D |
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E |
E |
E |
E |
D |
D |
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| Source | F88B0 | F89B0 |
|---|---|---|
| N1:JECLKCAS0M0_ECLKCASMUX_CORE_ECLKCASMUX4 | - | 1 |
| N1:JECLKCAS1M0_ECLKCASMUX_CORE_ECLKCASMUX4 | 1 | - |
| N1:JECLKSYNCM0_ECLKCASMUX_CORE_ECLKCASMUX4 | 1 | 1 |
| Source | F14B1 | F15B1 |
|---|---|---|
| N1W1:JECLKCAS0M0_ECLKCASMUX_CORE_ECLKCASMUX5 | - | 1 |
| N1W1:JECLKCAS1M0_ECLKCASMUX_CORE_ECLKCASMUX5 | 1 | - |
| N1W1:JECLKSYNCM0_ECLKCASMUX_CORE_ECLKCASMUX5 | 1 | 1 |
| Source | F101B1 | F102B1 |
|---|---|---|
| N1W1:JECLKCAS0M1_ECLKCASMUX_CORE_ECLKCASMUX5 | - | 1 |
| N1W1:JECLKCAS1M1_ECLKCASMUX_CORE_ECLKCASMUX5 | 1 | - |
| N1W1:JECLKSYNCM1_ECLKCASMUX_CORE_ECLKCASMUX5 | 1 | 1 |
| Source | F90B0 |
|---|---|
| N1W1:JECLKCAS1M2_ECLKCASMUX_CORE_ECLKCASMUX5 | - |
| N1W1:JECLKCAS0M2_ECLKCASMUX_CORE_ECLKCASMUX5 | 1 |
| N1W1:JECLKSYNCM2_ECLKCASMUX_CORE_ECLKCASMUX5 | 1 |
| Source | F95B0 | F98B0 |
|---|---|---|
| N1W1:JECLKCAS0M3_ECLKCASMUX_CORE_ECLKCASMUX5 | - | 1 |
| N1W1:JECLKCAS1M3_ECLKCASMUX_CORE_ECLKCASMUX5 | 1 | - |
| N1W1:JECLKSYNCM3_ECLKCASMUX_CORE_ECLKCASMUX5 | 1 | 1 |
| Source | F84B0 | F85B0 | F86B0 | F87B0 |
|---|---|---|---|---|
| G:JPCLKT1_ECLKBANK_CORE_ECLKBANK4 | - | 1 | - | - |
| G:JLRCLKOS4_ECLKBANK_CORE_ECLKBANK4 | - | 1 | - | 1 |
| G:JPCLKT0_ECLKBANK_CORE_ECLKBANK4 | - | 1 | 1 | - |
| G:JLRCLKOS2_ECLKBANK_CORE_ECLKBANK4 | - | 1 | 1 | 1 |
| G:JPCLKT3_ECLKBANK_CORE_ECLKBANK4 | 1 | - | - | 1 |
| N1:JECLKCIB0_ECLKBANK_CORE_ECLKBANK4 | 1 | - | 1 | - |
| G:JPCLKT2_ECLKBANK_CORE_ECLKBANK4 | 1 | - | 1 | 1 |
| G:JLRCLKOS_ECLKBANK_CORE_ECLKBANK4 | 1 | 1 | - | - |
| G:JLLCLKOS3_ECLKBANK_CORE_ECLKBANK4 | 1 | 1 | - | 1 |
| G:JLLCLKOS5_ECLKBANK_CORE_ECLKBANK4 | 1 | 1 | 1 | - |
| G:JLLCLKOP_ECLKBANK_CORE_ECLKBANK4 | 1 | 1 | 1 | 1 |
| Source | F9B1 | F10B1 | F11B1 | F12B1 |
|---|---|---|---|---|
| G:JPCLKT1_ECLKBANK_CORE_ECLKBANK5 | - | 1 | - | - |
| G:JLRCLKOS4_ECLKBANK_CORE_ECLKBANK5 | - | 1 | - | 1 |
| G:JPCLKT0_ECLKBANK_CORE_ECLKBANK5 | - | 1 | 1 | - |
| G:JLRCLKOS2_ECLKBANK_CORE_ECLKBANK5 | - | 1 | 1 | 1 |
| G:JPCLKT3_ECLKBANK_CORE_ECLKBANK5 | 1 | - | - | 1 |
| N1W1:JECLKCIB0_ECLKBANK_CORE_ECLKBANK5 | 1 | - | 1 | - |
| G:JPCLKT2_ECLKBANK_CORE_ECLKBANK5 | 1 | - | 1 | 1 |
| G:JLRCLKOS_ECLKBANK_CORE_ECLKBANK5 | 1 | 1 | - | - |
| G:JLLCLKOS3_ECLKBANK_CORE_ECLKBANK5 | 1 | 1 | - | 1 |
| G:JLLCLKOS5_ECLKBANK_CORE_ECLKBANK5 | 1 | 1 | 1 | - |
| G:JLLCLKOP_ECLKBANK_CORE_ECLKBANK5 | 1 | 1 | 1 | 1 |
| Source | F16B1 | F17B1 | F99B1 | F100B1 |
|---|---|---|---|---|
| G:JPCLKT1_ECLKBANK_CORE_ECLKBANK5 | - | 1 | - | - |
| G:JLRCLKOS5_ECLKBANK_CORE_ECLKBANK5 | - | 1 | - | 1 |
| G:JPCLKT0_ECLKBANK_CORE_ECLKBANK5 | - | 1 | 1 | - |
| G:JLRCLKOS3_ECLKBANK_CORE_ECLKBANK5 | - | 1 | 1 | 1 |
| G:JPCLKT3_ECLKBANK_CORE_ECLKBANK5 | 1 | - | - | 1 |
| N1W1:JECLKCIB1_ECLKBANK_CORE_ECLKBANK5 | 1 | - | 1 | - |
| G:JPCLKT2_ECLKBANK_CORE_ECLKBANK5 | 1 | - | 1 | 1 |
| G:JLRCLKOS2_ECLKBANK_CORE_ECLKBANK5 | 1 | 1 | - | - |
| G:JLLCLKOS_ECLKBANK_CORE_ECLKBANK5 | 1 | 1 | - | 1 |
| G:JLLCLKOS4_ECLKBANK_CORE_ECLKBANK5 | 1 | 1 | 1 | - |
| G:JLLCLKOP_ECLKBANK_CORE_ECLKBANK5 | 1 | 1 | 1 | 1 |
| Source | F91B0 | F92B0 | F93B0 | F94B0 |
|---|---|---|---|---|
| G:JPCLKT1_ECLKBANK_CORE_ECLKBANK5 | - | 1 | - | - |
| G:JLRCLKOS5_ECLKBANK_CORE_ECLKBANK5 | - | 1 | - | 1 |
| G:JPCLKT0_ECLKBANK_CORE_ECLKBANK5 | - | 1 | 1 | - |
| G:JLRCLKOS_ECLKBANK_CORE_ECLKBANK5 | - | 1 | 1 | 1 |
| G:JPCLKT3_ECLKBANK_CORE_ECLKBANK5 | 1 | - | - | 1 |
| N1W1:JECLKCIB3_ECLKBANK_CORE_ECLKBANK5 | 1 | - | 1 | - |
| G:JPCLKT2_ECLKBANK_CORE_ECLKBANK5 | 1 | - | 1 | 1 |
| G:JLRCLKOP_ECLKBANK_CORE_ECLKBANK5 | 1 | 1 | - | - |
| G:JLLCLKOS3_ECLKBANK_CORE_ECLKBANK5 | 1 | 1 | - | 1 |
| G:JLLCLKOS4_ECLKBANK_CORE_ECLKBANK5 | 1 | 1 | 1 | - |
| G:JLLCLKOS2_ECLKBANK_CORE_ECLKBANK5 | 1 | 1 | 1 | 1 |
| Source | F20B0 | F21B0 | F22B0 | F23B0 |
|---|---|---|---|---|
| G:JECLKDIV6_BMID_CORE_BMIDMUX | 0 | 1 | 0 | 0 |
| G:JLRCLKOS4_BMID_CORE_BMIDMUX | 0 | 1 | 0 | 1 |
| G:JECLKDIV0_BMID_CORE_BMIDMUX | 0 | 1 | 1 | 0 |
| G:JLRCLKOS2_BMID_CORE_BMIDMUX | 0 | 1 | 1 | 1 |
| G:JPCLKCIBB0_BMID_CORE_BMIDMUX | 1 | 0 | 0 | 1 |
| G:JECLKDIV10_BMID_CORE_BMIDMUX | 1 | 0 | 1 | 1 |
| G:JLLCLKOP_BMID_CORE_BMIDMUX | 1 | 1 | 0 | 0 |
| G:JPCLKT33_BMID_CORE_BMIDMUX | 1 | 1 | 0 | 1 |
| G:JPCLKT50_BMID_CORE_BMIDMUX | 1 | 1 | 1 | 0 |
| G:JPCLKT30_BMID_CORE_BMIDMUX | 1 | 1 | 1 | 1 |
| Source | F25B0 | F26B0 | F27B0 | F28B0 |
|---|---|---|---|---|
| G:JPCLKCIBB1_BMID_CORE_BMIDMUX | 0 | 1 | 0 | 0 |
| G:JECLKDIV3_BMID_CORE_BMIDMUX | 0 | 1 | 0 | 1 |
| G:JECLKDIV8_BMID_CORE_BMIDMUX | 0 | 1 | 1 | 0 |
| G:JLRCLKOS5_BMID_CORE_BMIDMUX | 0 | 1 | 1 | 1 |
| G:JPCLKCIBB4_BMID_CORE_BMIDMUX | 1 | 0 | 0 | 1 |
| G:JPCLKCIBB2_BMID_CORE_BMIDMUX | 1 | 0 | 1 | 1 |
| G:JLLCLKOS4_BMID_CORE_BMIDMUX | 1 | 1 | 0 | 0 |
| G:JPCLKT42_BMID_CORE_BMIDMUX | 1 | 1 | 0 | 1 |
| G:JPCLKT51_BMID_CORE_BMIDMUX | 1 | 1 | 1 | 0 |
| G:JPCLKT31_BMID_CORE_BMIDMUX | 1 | 1 | 1 | 1 |
| Source | F30B0 | F31B0 | F32B0 | F33B0 |
|---|---|---|---|---|
| G:JECLKDIV9_BMID_CORE_BMIDMUX | 0 | 1 | 0 | 0 |
| G:JLRCLKOS3_BMID_CORE_BMIDMUX | 0 | 1 | 0 | 1 |
| G:JECLKDIV1_BMID_CORE_BMIDMUX | 0 | 1 | 1 | 0 |
| G:JLRCLKOP_BMID_CORE_BMIDMUX | 0 | 1 | 1 | 1 |
| G:JPCLKCIBB5_BMID_CORE_BMIDMUX | 1 | 0 | 0 | 1 |
| G:JPCLKCIBB1_BMID_CORE_BMIDMUX | 1 | 0 | 1 | 1 |
| G:JLLCLKOS3_BMID_CORE_BMIDMUX | 1 | 1 | 0 | 0 |
| G:JPCLKT41_BMID_CORE_BMIDMUX | 1 | 1 | 0 | 1 |
| G:JPCLKT53_BMID_CORE_BMIDMUX | 1 | 1 | 1 | 0 |
| G:JPCLKT32_BMID_CORE_BMIDMUX | 1 | 1 | 1 | 1 |
| Source | F35B0 | F36B0 | F37B0 | F38B0 |
|---|---|---|---|---|
| G:JECLKDIV11_BMID_CORE_BMIDMUX | 0 | 1 | 0 | 0 |
| G:JECLKDIV2_BMID_CORE_BMIDMUX | 0 | 1 | 0 | 1 |
| G:JECLKDIV6_BMID_CORE_BMIDMUX | 0 | 1 | 1 | 0 |
| G:JLLCLKOS5_BMID_CORE_BMIDMUX | 0 | 1 | 1 | 1 |
| G:JPCLKCIBB3_BMID_CORE_BMIDMUX | 1 | 0 | 1 | 1 |
| G:JLLCLKOS2_BMID_CORE_BMIDMUX | 1 | 1 | 0 | 0 |
| G:JPCLKT33_BMID_CORE_BMIDMUX | 1 | 1 | 0 | 1 |
| G:JPCLKT52_BMID_CORE_BMIDMUX | 1 | 1 | 1 | 0 |
| G:JPCLKT30_BMID_CORE_BMIDMUX | 1 | 1 | 1 | 1 |
| Source | F40B0 | F41B0 | F42B0 | F43B0 |
|---|---|---|---|---|
| G:JECLKDIV10_BMID_CORE_BMIDMUX | 0 | 1 | 0 | 0 |
| G:JECLKDIV0_BMID_CORE_BMIDMUX | 0 | 1 | 0 | 1 |
| G:JECLKDIV3_BMID_CORE_BMIDMUX | 0 | 1 | 1 | 0 |
| G:JLRCLKOS_BMID_CORE_BMIDMUX | 0 | 1 | 1 | 1 |
| G:JPCLKCIBB2_BMID_CORE_BMIDMUX | 1 | 0 | 0 | 1 |
| G:JPCLKCIBB0_BMID_CORE_BMIDMUX | 1 | 0 | 1 | 1 |
| G:JLLCLKOP_BMID_CORE_BMIDMUX | 1 | 1 | 0 | 0 |
| G:JPCLKT43_BMID_CORE_BMIDMUX | 1 | 1 | 0 | 1 |
| G:JPCLKT52_BMID_CORE_BMIDMUX | 1 | 1 | 1 | 0 |
| G:JPCLKT40_BMID_CORE_BMIDMUX | 1 | 1 | 1 | 1 |
| Source | F45B0 | F46B0 | F47B0 | F48B0 |
|---|---|---|---|---|
| G:JPCLKCIBB2_BMID_CORE_BMIDMUX | 0 | 1 | 0 | 0 |
| G:JECLKDIV7_BMID_CORE_BMIDMUX | 0 | 1 | 0 | 1 |
| G:JECLKDIV10_BMID_CORE_BMIDMUX | 0 | 1 | 1 | 0 |
| G:JECLKDIV4_BMID_CORE_BMIDMUX | 0 | 1 | 1 | 1 |
| G:JPCLKCIBB4_BMID_CORE_BMIDMUX | 1 | 0 | 1 | 1 |
| G:JLRCLKOP_BMID_CORE_BMIDMUX | 1 | 1 | 0 | 0 |
| G:JPCLKT41_BMID_CORE_BMIDMUX | 1 | 1 | 0 | 1 |
| G:JLLCLKOS_BMID_CORE_BMIDMUX | 1 | 1 | 1 | 0 |
| G:JPCLKT32_BMID_CORE_BMIDMUX | 1 | 1 | 1 | 1 |
| Source | F50B0 | F51B0 | F52B0 | F53B0 |
|---|---|---|---|---|
| G:JPCLKCIBB1_BMID_CORE_BMIDMUX | 0 | 1 | 0 | 0 |
| G:JECLKDIV5_BMID_CORE_BMIDMUX | 0 | 1 | 0 | 1 |
| G:JECLKDIV7_BMID_CORE_BMIDMUX | 0 | 1 | 1 | 0 |
| G:JLRCLKOS_BMID_CORE_BMIDMUX | 0 | 1 | 1 | 1 |
| G:JPCLKCIBB5_BMID_CORE_BMIDMUX | 1 | 0 | 1 | 1 |
| G:JLLCLKOS_BMID_CORE_BMIDMUX | 1 | 1 | 0 | 0 |
| G:JPCLKT42_BMID_CORE_BMIDMUX | 1 | 1 | 0 | 1 |
| G:JPCLKT51_BMID_CORE_BMIDMUX | 1 | 1 | 1 | 0 |
| G:JPCLKT31_BMID_CORE_BMIDMUX | 1 | 1 | 1 | 1 |
| Source | F55B0 | F56B0 | F57B0 | F58B0 |
|---|---|---|---|---|
| G:JECLKDIV5_BMID_CORE_BMIDMUX | 0 | 1 | 0 | 0 |
| G:JLRCLKOS4_BMID_CORE_BMIDMUX | 0 | 1 | 0 | 1 |
| G:JECLKDIV1_BMID_CORE_BMIDMUX | 0 | 1 | 1 | 0 |
| G:JLRCLKOS2_BMID_CORE_BMIDMUX | 0 | 1 | 1 | 1 |
| G:JPCLKCIBB0_BMID_CORE_BMIDMUX | 1 | 0 | 0 | 1 |
| G:JECLKDIV9_BMID_CORE_BMIDMUX | 1 | 0 | 1 | 1 |
| G:JLLCLKOS3_BMID_CORE_BMIDMUX | 1 | 1 | 0 | 0 |
| G:JPCLKT43_BMID_CORE_BMIDMUX | 1 | 1 | 0 | 1 |
| G:JLLCLKOP_BMID_CORE_BMIDMUX | 1 | 1 | 1 | 0 |
| G:JPCLKT40_BMID_CORE_BMIDMUX | 1 | 1 | 1 | 1 |
| Source | F60B0 | F61B0 | F62B0 | F63B0 |
|---|---|---|---|---|
| G:JECLKDIV6_BMID_CORE_BMIDMUX | 0 | 1 | 0 | 0 |
| G:JLRCLKOS5_BMID_CORE_BMIDMUX | 0 | 1 | 0 | 1 |
| G:JECLKDIV2_BMID_CORE_BMIDMUX | 0 | 1 | 1 | 0 |
| G:JLRCLKOS3_BMID_CORE_BMIDMUX | 0 | 1 | 1 | 1 |
| G:JPCLKCIBB3_BMID_CORE_BMIDMUX | 1 | 0 | 0 | 1 |
| G:JECLKDIV11_BMID_CORE_BMIDMUX | 1 | 0 | 1 | 1 |
| G:JLLCLKOS5_BMID_CORE_BMIDMUX | 1 | 1 | 0 | 0 |
| G:JPCLKT50_BMID_CORE_BMIDMUX | 1 | 1 | 0 | 1 |
| G:JLLCLKOS2_BMID_CORE_BMIDMUX | 1 | 1 | 1 | 0 |
| G:JPCLKT33_BMID_CORE_BMIDMUX | 1 | 1 | 1 | 1 |
DCC bypassed (0) or used as gate (1)
| Value | F10B0 |
|---|---|
| 0 | - |
| 1 | 1 |
DCC bypassed (0) or used as gate (1)
| Value | F11B0 |
|---|---|
| 0 | - |
| 1 | 1 |
DCC bypassed (0) or used as gate (1)
| Value | F12B0 |
|---|---|
| 0 | - |
| 1 | 1 |
DCC bypassed (0) or used as gate (1)
| Value | F13B0 |
|---|---|
| 0 | - |
| 1 | 1 |
DCC bypassed (0) or used as gate (1)
| Value | F14B0 |
|---|---|
| 0 | - |
| 1 | 1 |
DCC bypassed (0) or used as gate (1)
| Value | F15B0 |
|---|---|
| 0 | - |
| 1 | 1 |
DCC bypassed (0) or used as gate (1)
| Value | F16B0 |
|---|---|
| 0 | - |
| 1 | 1 |
DCC bypassed (0) or used as gate (1)
| Value | F17B0 |
|---|---|
| 0 | - |
| 1 | 1 |
DCC bypassed (0) or used as gate (1)
| Value | F18B0 |
|---|---|
| 0 | - |
| 1 | 1 |
ECLKDIV divide value
| Value | F25B1 | F34B1 |
|---|---|---|
| 2 | 1 | - |
| 3P5 | - | 1 |
| 4 | - | - |
| 5 | - | - |
| DISABLE | - | - |
ECLKDIV divide value
| Value | F26B1 | F35B1 |
|---|---|---|
| 2 | 1 | - |
| 3P5 | - | 1 |
| 4 | - | - |
| 5 | - | - |
| DISABLE | - | - |
ECLKDIV divide value
| Value | F99B0 | F104B1 |
|---|---|---|
| 2 | 1 | - |
| 3P5 | - | 1 |
| 4 | - | - |
| 5 | - | - |
| DISABLE | - | - |
ECLKDIV GSR mask
| Value | F59B1 |
|---|---|
| DISABLED | 1 |
| ENABLED | - |
ECLKDIV divide value
| Value | F101B0 | F103B1 |
|---|---|---|
| 2 | 1 | - |
| 3P5 | - | 1 |
| 4 | - | - |
| 5 | - | - |
| DISABLE | - | - |
ECLKDIV GSR mask
| Value | F60B1 |
|---|---|
| DISABLED | 1 |
| ENABLED | - |
ECLKDIV divide value
| Value | F29B1 | F51B1 | F94B1 | F102B0 |
|---|---|---|---|---|
| 2 | - | - | - | 1 |
| 3P5 | - | - | 1 | - |
| 4 | 1 | - | - | - |
| 5 | - | 1 | - | - |
| DISABLE | - | - | - | - |
ECLKDIV GSR mask
| Value | F61B1 |
|---|---|
| DISABLED | 1 |
| ENABLED | - |
ECLKDIV divide value
| Value | F30B1 | F52B1 | F93B1 | F103B0 |
|---|---|---|---|---|
| 2 | - | - | - | 1 |
| 3P5 | - | - | 1 | - |
| 4 | 1 | - | - | - |
| 5 | - | 1 | - | - |
| DISABLE | - | - | - | - |
ECLKDIV GSR mask
| Value | F62B1 |
|---|---|
| DISABLED | 1 |
| ENABLED | - |
ECLKDIV divide value
| Value | F31B1 | F55B1 | F92B1 | F104B0 |
|---|---|---|---|---|
| 2 | - | - | - | 1 |
| 3P5 | - | - | 1 | - |
| 4 | 1 | - | - | - |
| 5 | - | 1 | - | - |
| DISABLE | - | - | - | - |
ECLKDIV GSR mask
| Value | F65B1 |
|---|---|
| DISABLED | 1 |
| ENABLED | - |
ECLKDIV divide value
| Value | F32B1 | F56B1 | F91B1 | F105B0 |
|---|---|---|---|---|
| 2 | - | - | - | 1 |
| 3P5 | - | - | 1 | - |
| 4 | 1 | - | - | - |
| 5 | - | 1 | - | - |
| DISABLE | - | - | - | - |
ECLKDIV GSR mask
| Value | F66B1 |
|---|---|
| DISABLED | 1 |
| ENABLED | - |
ECLKSYNC stop control enable
| Value | F75B1 |
|---|---|
| DISABLE | - |
| ENABLE | 1 |
ECLKSYNC stop control enable
| Value | F72B1 |
|---|---|
| DISABLE | - |
| ENABLE | 1 |
ECLKSYNC stop control enable
| Value | F69B1 |
|---|---|
| DISABLE | - |
| ENABLE | 1 |
ECLKSYNC stop control enable
| Value | F76B1 |
|---|---|
| DISABLE | - |
| ENABLE | 1 |
ECLKSYNC stop control enable
| Value | F86B1 |
|---|---|
| DISABLE | - |
| ENABLE | 1 |
ECLKSYNC stop control enable
| Value | F87B1 |
|---|---|
| DISABLE | - |
| ENABLE | 1 |
| Source | Sink | |
|---|---|---|
| N1:JDIVOUT_ECLKDIV_CORE_ECLKDIVB4_0 | → | G:JECLKDIV4_BMID_CORE_BMIDMUX |
| N1:JDIVOUT_ECLKDIV_CORE_ECLKDIVB4_1 | → | G:JECLKDIV5_BMID_CORE_BMIDMUX |
| N1:JDIVOUT_ECLKDIV_CORE_ECLKDIVB4_2 | → | G:JECLKDIV6_BMID_CORE_BMIDMUX |
| N1:JDIVOUT_ECLKDIV_CORE_ECLKDIVB4_3 | → | G:JECLKDIV7_BMID_CORE_BMIDMUX |
| N1W2:JCIBMUXOUTD7 | → | G:JPCLKCIBB0_BMID_CORE_BMIDMUX |
| N1W1:JCIBMUXOUTD7 | → | G:JPCLKCIBB1_BMID_CORE_BMIDMUX |
| N1:JCIBMUXOUTD7 | → | G:JPCLKCIBB2_BMID_CORE_BMIDMUX |
| N1E1:JCIBMUXOUTD7 | → | G:JPCLKCIBB3_BMID_CORE_BMIDMUX |
| N1E2:JCIBMUXOUTD7 | → | G:JPCLKCIBB4_BMID_CORE_BMIDMUX |
| N1E3:JCIBMUXOUTD7 | → | G:JPCLKCIBB5_BMID_CORE_BMIDMUX |
| N1E4:JCLKOUT_DLLDEL_CORE_I0 | → | G:JPCLKT0_ECLKBANK_CORE_ECLKBANK4 |
| N1W3:JCLKOUT_DLLDEL_CORE_I0 | → | G:JPCLKT2_ECLKBANK_CORE_ECLKBANK4 |
| N1E5:JCLKOUT_DLLDEL_CORE_I0 | → | G:JPCLKT30_BMID_CORE_BMIDMUX |
| E9:JINCK_IOLOGIC_CORE_I_GEARING_PIC_TOP_A | → | G:JPCLKT31_BMID_CORE_BMIDMUX |
| E9:JPADDI_DIFFIO18_CORE_IOA | → | G:JPCLKT31_BMID_CORE_BMIDMUX |
| N1E6:JCLKOUT_DLLDEL_CORE_I0 | → | G:JPCLKT32_BMID_CORE_BMIDMUX |
| E25:JINCK_IOLOGIC_CORE_I_GEARING_PIC_TOP_A | → | G:JPCLKT33_BMID_CORE_BMIDMUX |
| E25:JPADDI_DIFFIO18_CORE_IOA | → | G:JPCLKT33_BMID_CORE_BMIDMUX |
| N1E4:JCLKOUT_DLLDEL_CORE_I0 | → | G:JPCLKT40_BMID_CORE_BMIDMUX |
| W9:JINCK_IOLOGIC_CORE_I_GEARING_PIC_TOP_A | → | G:JPCLKT41_BMID_CORE_BMIDMUX |
| W9:JPADDI_DIFFIO18_CORE_IOA | → | G:JPCLKT41_BMID_CORE_BMIDMUX |
| N1W3:JCLKOUT_DLLDEL_CORE_I0 | → | G:JPCLKT42_BMID_CORE_BMIDMUX |
| W31:JINCK_IOLOGIC_CORE_I_GEARING_PIC_TOP_A | → | G:JPCLKT43_BMID_CORE_BMIDMUX |
| W31:JPADDI_DIFFIO18_CORE_IOA | → | G:JPCLKT43_BMID_CORE_BMIDMUX |
| N1W5:JCLKOUT_DLLDEL_CORE_I0 | → | G:JPCLKT50_BMID_CORE_BMIDMUX |
| W41:JINCK_IOLOGIC_CORE_I_GEARING_PIC_TOP_A | → | G:JPCLKT51_BMID_CORE_BMIDMUX |
| W41:JPADDI_DIFFIO18_CORE_IOA | → | G:JPCLKT51_BMID_CORE_BMIDMUX |
| N1W4:JCLKOUT_DLLDEL_CORE_I0 | → | G:JPCLKT52_BMID_CORE_BMIDMUX |
| W37:JINCK_IOLOGIC_CORE_I_GEARING_PIC_TOP_A | → | G:JPCLKT53_BMID_CORE_BMIDMUX |
| W37:JPADDI_DIFFIO18_CORE_IOA | → | G:JPCLKT53_BMID_CORE_BMIDMUX |
| N1:JCIBMUXOUTA0 | → | G:JTESTINP0_BMID_CORE_BMIDMUX |
| N1:JCIBMUXOUTA1 | → | G:JTESTINP1_BMID_CORE_BMIDMUX |
| N1:JCIBMUXOUTA2 | → | G:JTESTINP2_BMID_CORE_BMIDMUX |
| N1:JCIBMUXOUTA3 | → | G:JTESTINP3_BMID_CORE_BMIDMUX |
| JCLKO_DCC_DCC0 | → | G:JVPFN0_CMUX_CORE_CMUX0 |
| JCLKO_DCC_DCC0 | → | G:JVPFN0_CMUX_CORE_CMUX1 |
| JCLKO_DCC_DCC0 | → | G:JVPFN0_DCSMUX_CORE_DCSMUX0 |
| JCLKO_DCC_DCC0 | → | G:JVPFN0_DCSMUX_CORE_DCSMUX1 |
| JCLKO_DCC_DCC10 | → | G:JVPFN10_CMUX_CORE_CMUX0 |
| JCLKO_DCC_DCC10 | → | G:JVPFN10_CMUX_CORE_CMUX1 |
| JCLKO_DCC_DCC10 | → | G:JVPFN10_DCSMUX_CORE_DCSMUX0 |
| JCLKO_DCC_DCC10 | → | G:JVPFN10_DCSMUX_CORE_DCSMUX1 |
| JCLKO_DCC_DCC11 | → | G:JVPFN11_CMUX_CORE_CMUX0 |
| JCLKO_DCC_DCC11 | → | G:JVPFN11_CMUX_CORE_CMUX1 |
| JCLKO_DCC_DCC11 | → | G:JVPFN11_DCSMUX_CORE_DCSMUX0 |
| JCLKO_DCC_DCC11 | → | G:JVPFN11_DCSMUX_CORE_DCSMUX1 |
| JCLKO_DCC_DCC12 | → | G:JVPFN12_CMUX_CORE_CMUX0 |
| JCLKO_DCC_DCC12 | → | G:JVPFN12_CMUX_CORE_CMUX1 |
| JCLKO_DCC_DCC12 | → | G:JVPFN12_DCSMUX_CORE_DCSMUX0 |
| JCLKO_DCC_DCC12 | → | G:JVPFN12_DCSMUX_CORE_DCSMUX1 |
| JCLKO_DCC_DCC13 | → | G:JVPFN13_CMUX_CORE_CMUX0 |
| JCLKO_DCC_DCC13 | → | G:JVPFN13_CMUX_CORE_CMUX1 |
| JCLKO_DCC_DCC13 | → | G:JVPFN13_DCSMUX_CORE_DCSMUX0 |
| JCLKO_DCC_DCC13 | → | G:JVPFN13_DCSMUX_CORE_DCSMUX1 |
| JCLKO_DCC_DCC14 | → | G:JVPFN14_CMUX_CORE_CMUX0 |
| JCLKO_DCC_DCC14 | → | G:JVPFN14_CMUX_CORE_CMUX1 |
| JCLKO_DCC_DCC14 | → | G:JVPFN14_DCSMUX_CORE_DCSMUX0 |
| JCLKO_DCC_DCC14 | → | G:JVPFN14_DCSMUX_CORE_DCSMUX1 |
| JCLKO_DCC_DCC15 | → | G:JVPFN15_CMUX_CORE_CMUX0 |
| JCLKO_DCC_DCC15 | → | G:JVPFN15_CMUX_CORE_CMUX1 |
| JCLKO_DCC_DCC15 | → | G:JVPFN15_DCSMUX_CORE_DCSMUX0 |
| JCLKO_DCC_DCC15 | → | G:JVPFN15_DCSMUX_CORE_DCSMUX1 |
| JCLKO_DCC_DCC16 | → | G:JVPFN16_CMUX_CORE_CMUX0 |
| JCLKO_DCC_DCC16 | → | G:JVPFN16_CMUX_CORE_CMUX1 |
| JCLKO_DCC_DCC16 | → | G:JVPFN16_DCSMUX_CORE_DCSMUX0 |
| JCLKO_DCC_DCC16 | → | G:JVPFN16_DCSMUX_CORE_DCSMUX1 |
| JCLKO_DCC_DCC17 | → | G:JVPFN17_CMUX_CORE_CMUX0 |
| JCLKO_DCC_DCC17 | → | G:JVPFN17_CMUX_CORE_CMUX1 |
| JCLKO_DCC_DCC17 | → | G:JVPFN17_DCSMUX_CORE_DCSMUX0 |
| JCLKO_DCC_DCC17 | → | G:JVPFN17_DCSMUX_CORE_DCSMUX1 |
| JCLKO_DCC_DCC1 | → | G:JVPFN1_CMUX_CORE_CMUX0 |
| JCLKO_DCC_DCC1 | → | G:JVPFN1_CMUX_CORE_CMUX1 |
| JCLKO_DCC_DCC1 | → | G:JVPFN1_DCSMUX_CORE_DCSMUX0 |
| JCLKO_DCC_DCC1 | → | G:JVPFN1_DCSMUX_CORE_DCSMUX1 |
| JCLKO_DCC_DCC2 | → | G:JVPFN2_CMUX_CORE_CMUX0 |
| JCLKO_DCC_DCC2 | → | G:JVPFN2_CMUX_CORE_CMUX1 |
| JCLKO_DCC_DCC2 | → | G:JVPFN2_DCSMUX_CORE_DCSMUX0 |
| JCLKO_DCC_DCC2 | → | G:JVPFN2_DCSMUX_CORE_DCSMUX1 |
| JCLKO_DCC_DCC3 | → | G:JVPFN3_CMUX_CORE_CMUX0 |
| JCLKO_DCC_DCC3 | → | G:JVPFN3_CMUX_CORE_CMUX1 |
| JCLKO_DCC_DCC3 | → | G:JVPFN3_DCSMUX_CORE_DCSMUX0 |
| JCLKO_DCC_DCC3 | → | G:JVPFN3_DCSMUX_CORE_DCSMUX1 |
| JCLKO_DCC_DCC4 | → | G:JVPFN4_CMUX_CORE_CMUX0 |
| JCLKO_DCC_DCC4 | → | G:JVPFN4_CMUX_CORE_CMUX1 |
| JCLKO_DCC_DCC4 | → | G:JVPFN4_DCSMUX_CORE_DCSMUX0 |
| JCLKO_DCC_DCC4 | → | G:JVPFN4_DCSMUX_CORE_DCSMUX1 |
| JCLKO_DCC_DCC5 | → | G:JVPFN5_CMUX_CORE_CMUX0 |
| JCLKO_DCC_DCC5 | → | G:JVPFN5_CMUX_CORE_CMUX1 |
| JCLKO_DCC_DCC5 | → | G:JVPFN5_DCSMUX_CORE_DCSMUX0 |
| JCLKO_DCC_DCC5 | → | G:JVPFN5_DCSMUX_CORE_DCSMUX1 |
| JCLKO_DCC_DCC6 | → | G:JVPFN6_CMUX_CORE_CMUX0 |
| JCLKO_DCC_DCC6 | → | G:JVPFN6_CMUX_CORE_CMUX1 |
| JCLKO_DCC_DCC6 | → | G:JVPFN6_DCSMUX_CORE_DCSMUX0 |
| JCLKO_DCC_DCC6 | → | G:JVPFN6_DCSMUX_CORE_DCSMUX1 |
| JCLKO_DCC_DCC7 | → | G:JVPFN7_CMUX_CORE_CMUX0 |
| JCLKO_DCC_DCC7 | → | G:JVPFN7_CMUX_CORE_CMUX1 |
| JCLKO_DCC_DCC7 | → | G:JVPFN7_DCSMUX_CORE_DCSMUX0 |
| JCLKO_DCC_DCC7 | → | G:JVPFN7_DCSMUX_CORE_DCSMUX1 |
| JCLKO_DCC_DCC8 | → | G:JVPFN8_CMUX_CORE_CMUX0 |
| JCLKO_DCC_DCC8 | → | G:JVPFN8_CMUX_CORE_CMUX1 |
| JCLKO_DCC_DCC8 | → | G:JVPFN8_DCSMUX_CORE_DCSMUX0 |
| JCLKO_DCC_DCC8 | → | G:JVPFN8_DCSMUX_CORE_DCSMUX1 |
| JCLKO_DCC_DCC9 | → | G:JVPFN9_CMUX_CORE_CMUX0 |
| JCLKO_DCC_DCC9 | → | G:JVPFN9_CMUX_CORE_CMUX1 |
| JCLKO_DCC_DCC9 | → | G:JVPFN9_DCSMUX_CORE_DCSMUX0 |
| JCLKO_DCC_DCC9 | → | G:JVPFN9_DCSMUX_CORE_DCSMUX1 |
| N1:JCIBMUXOUTC0 | → | JCE_DCC_DCC0 |
| N1:JCIBMUXOUTC1 | → | JCE_DCC_DCC1 |
| N1E1:JCIBMUXOUTA6 | → | JCE_DCC_DCC10 |
| N1E1:JCIBMUXOUTA7 | → | JCE_DCC_DCC11 |
| N1E1:JCIBMUXOUTC0 | → | JCE_DCC_DCC12 |
| N1E1:JCIBMUXOUTC1 | → | JCE_DCC_DCC13 |
| N1E1:JCIBMUXOUTC2 | → | JCE_DCC_DCC14 |
| N1E1:JCIBMUXOUTC3 | → | JCE_DCC_DCC15 |
| N1E1:JCIBMUXOUTC4 | → | JCE_DCC_DCC16 |
| N1E1:JCIBMUXOUTC5 | → | JCE_DCC_DCC17 |
| N1:JCIBMUXOUTC2 | → | JCE_DCC_DCC2 |
| N1:JCIBMUXOUTC3 | → | JCE_DCC_DCC3 |
| N1:JCIBMUXOUTC4 | → | JCE_DCC_DCC4 |
| N1:JCIBMUXOUTC5 | → | JCE_DCC_DCC5 |
| N1:JCIBMUXOUTC6 | → | JCE_DCC_DCC6 |
| N1:JCIBMUXOUTC7 | → | JCE_DCC_DCC7 |
| N1E1:JCIBMUXOUTA4 | → | JCE_DCC_DCC8 |
| N1E1:JCIBMUXOUTA5 | → | JCE_DCC_DCC9 |
| G:JVPFN0_BMID_CORE_BMIDMUX | → | JCLKI_DCC_DCC0 |
| G:JVPFN1_BMID_CORE_BMIDMUX | → | JCLKI_DCC_DCC1 |
| G:JVPFN10_BMID_CORE_BMIDMUX | → | JCLKI_DCC_DCC10 |
| G:JVPFN11_BMID_CORE_BMIDMUX | → | JCLKI_DCC_DCC11 |
| G:JVPFN12_BMID_CORE_BMIDMUX | → | JCLKI_DCC_DCC12 |
| G:JVPFN13_BMID_CORE_BMIDMUX | → | JCLKI_DCC_DCC13 |
| G:JVPFN14_BMID_CORE_BMIDMUX | → | JCLKI_DCC_DCC14 |
| G:JVPFN15_BMID_CORE_BMIDMUX | → | JCLKI_DCC_DCC15 |
| G:JVPFN16_BMID_CORE_BMIDMUX | → | JCLKI_DCC_DCC16 |
| G:JVPFN17_BMID_CORE_BMIDMUX | → | JCLKI_DCC_DCC17 |
| G:JVPFN2_BMID_CORE_BMIDMUX | → | JCLKI_DCC_DCC2 |
| G:JVPFN3_BMID_CORE_BMIDMUX | → | JCLKI_DCC_DCC3 |
| G:JVPFN4_BMID_CORE_BMIDMUX | → | JCLKI_DCC_DCC4 |
| G:JVPFN5_BMID_CORE_BMIDMUX | → | JCLKI_DCC_DCC5 |
| G:JVPFN6_BMID_CORE_BMIDMUX | → | JCLKI_DCC_DCC6 |
| G:JVPFN7_BMID_CORE_BMIDMUX | → | JCLKI_DCC_DCC7 |
| G:JVPFN8_BMID_CORE_BMIDMUX | → | JCLKI_DCC_DCC8 |
| G:JVPFN9_BMID_CORE_BMIDMUX | → | JCLKI_DCC_DCC9 |
| JCLKI_DCC_DCC0 | → | JCLKO_DCC_DCC0 |
| JCLKI_DCC_DCC1 | → | JCLKO_DCC_DCC1 |
| JCLKI_DCC_DCC10 | → | JCLKO_DCC_DCC10 |
| JCLKI_DCC_DCC11 | → | JCLKO_DCC_DCC11 |
| JCLKI_DCC_DCC12 | → | JCLKO_DCC_DCC12 |
| JCLKI_DCC_DCC13 | → | JCLKO_DCC_DCC13 |
| JCLKI_DCC_DCC14 | → | JCLKO_DCC_DCC14 |
| JCLKI_DCC_DCC15 | → | JCLKO_DCC_DCC15 |
| JCLKI_DCC_DCC16 | → | JCLKO_DCC_DCC16 |
| JCLKI_DCC_DCC17 | → | JCLKO_DCC_DCC17 |
| JCLKI_DCC_DCC2 | → | JCLKO_DCC_DCC2 |
| JCLKI_DCC_DCC3 | → | JCLKO_DCC_DCC3 |
| JCLKI_DCC_DCC4 | → | JCLKO_DCC_DCC4 |
| JCLKI_DCC_DCC5 | → | JCLKO_DCC_DCC5 |
| JCLKI_DCC_DCC6 | → | JCLKO_DCC_DCC6 |
| JCLKI_DCC_DCC7 | → | JCLKO_DCC_DCC7 |
| JCLKI_DCC_DCC8 | → | JCLKO_DCC_DCC8 |
| JCLKI_DCC_DCC9 | → | JCLKO_DCC_DCC9 |
| N1E2:JLSR0 | → | N1:JDIVRST_ECLKDIV_CORE_ECLKDIVB4_0 |
| N1E2:JLSR1 | → | N1:JDIVRST_ECLKDIV_CORE_ECLKDIVB4_1 |
| N1E1:JLSR0 | → | N1:JDIVRST_ECLKDIV_CORE_ECLKDIVB4_2 |
| N1E1:JLSR1 | → | N1:JDIVRST_ECLKDIV_CORE_ECLKDIVB4_3 |
| N1E1:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC3_0 | → | N1:JECLKCAS0M0_ECLKCASMUX_CORE_ECLKCASMUX4 |
| N1E1:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC3_1 | → | N1:JECLKCAS0M1_ECLKCASMUX_CORE_ECLKCASMUX4 |
| N1E1:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC3_2 | → | N1:JECLKCAS0M2_ECLKCASMUX_CORE_ECLKCASMUX4 |
| N1E1:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC3_3 | → | N1:JECLKCAS0M3_ECLKCASMUX_CORE_ECLKCASMUX4 |
| N1W1:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC5_0 | → | N1:JECLKCAS1M0_ECLKCASMUX_CORE_ECLKCASMUX4 |
| N1W1:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC5_1 | → | N1:JECLKCAS1M1_ECLKCASMUX_CORE_ECLKCASMUX4 |
| N1W1:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC5_2 | → | N1:JECLKCAS1M2_ECLKCASMUX_CORE_ECLKCASMUX4 |
| N1W1:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC5_3 | → | N1:JECLKCAS1M3_ECLKCASMUX_CORE_ECLKCASMUX4 |
| N1:JCIBMUXOUTB4 | → | N1:JECLKCIB0_ECLKBANK_CORE_ECLKBANK4 |
| N1:JCIBMUXOUTB5 | → | N1:JECLKCIB1_ECLKBANK_CORE_ECLKBANK4 |
| N1:JCIBMUXOUTB6 | → | N1:JECLKCIB2_ECLKBANK_CORE_ECLKBANK4 |
| N1:JCIBMUXOUTB7 | → | N1:JECLKCIB3_ECLKBANK_CORE_ECLKBANK4 |
| G:JECLKOUT0_ECLKCASMUX_CORE_ECLKCASMUX4 | → | N1:JECLKIN_ECLKDIV_CORE_ECLKDIVB4_0 |
| G:JECLKOUT1_ECLKCASMUX_CORE_ECLKCASMUX4 | → | N1:JECLKIN_ECLKDIV_CORE_ECLKDIVB4_1 |
| G:JECLKOUT2_ECLKCASMUX_CORE_ECLKCASMUX4 | → | N1:JECLKIN_ECLKDIV_CORE_ECLKDIVB4_2 |
| G:JECLKOUT3_ECLKCASMUX_CORE_ECLKCASMUX4 | → | N1:JECLKIN_ECLKDIV_CORE_ECLKDIVB4_3 |
| G:JMUXIN0_ECLKBANK_CORE_ECLKBANK4 | → | N1:JECLKIN_ECLKSYNC_CORE_ECLKSYNC4_0 |
| G:JMUXIN1_ECLKBANK_CORE_ECLKBANK4 | → | N1:JECLKIN_ECLKSYNC_CORE_ECLKSYNC4_1 |
| G:JMUXIN2_ECLKBANK_CORE_ECLKBANK4 | → | N1:JECLKIN_ECLKSYNC_CORE_ECLKSYNC4_2 |
| G:JMUXIN3_ECLKBANK_CORE_ECLKBANK4 | → | N1:JECLKIN_ECLKSYNC_CORE_ECLKSYNC4_3 |
| N1:JECLKIN_ECLKSYNC_CORE_ECLKSYNC4_0 | → | N1:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC4_0 |
| N1:JECLKIN_ECLKSYNC_CORE_ECLKSYNC4_1 | → | N1:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC4_1 |
| N1:JECLKIN_ECLKSYNC_CORE_ECLKSYNC4_2 | → | N1:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC4_2 |
| N1:JECLKIN_ECLKSYNC_CORE_ECLKSYNC4_3 | → | N1:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC4_3 |
| N1:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC4_0 | → | N1:JECLKSYNCM0_ECLKCASMUX_CORE_ECLKCASMUX4 |
| N1:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC4_1 | → | N1:JECLKSYNCM1_ECLKCASMUX_CORE_ECLKCASMUX4 |
| N1:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC4_2 | → | N1:JECLKSYNCM2_ECLKCASMUX_CORE_ECLKCASMUX4 |
| N1:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC4_3 | → | N1:JECLKSYNCM3_ECLKCASMUX_CORE_ECLKCASMUX4 |
| N1E2:JCIBMUXOUTC6 | → | N1:JSLIP_ECLKDIV_CORE_ECLKDIVB4_0 |
| N1E2:JCIBMUXOUTC7 | → | N1:JSLIP_ECLKDIV_CORE_ECLKDIVB4_1 |
| N1E2:JCIBMUXOUTD0 | → | N1:JSLIP_ECLKDIV_CORE_ECLKDIVB4_2 |
| N1E2:JCIBMUXOUTD1 | → | N1:JSLIP_ECLKDIV_CORE_ECLKDIVB4_3 |
| N1E1:JCIBMUXOUTB2 | → | N1:JSTOP_ECLKSYNC_CORE_ECLKSYNC4_0 |
| N1E1:JCIBMUXOUTD3 | → | N1:JSTOP_ECLKSYNC_CORE_ECLKSYNC4_1 |
| N1E1:JCIBMUXOUTB1 | → | N1:JSTOP_ECLKSYNC_CORE_ECLKSYNC4_2 |
| N1E1:JCIBMUXOUTB6 | → | N1:JSTOP_ECLKSYNC_CORE_ECLKSYNC4_3 |
| N1W1:JCIBMUXOUTA6 | → | N1:JTESTINP0_ECLKBANK_CORE_ECLKBANK4 |
| N1W1:JCIBMUXOUTB2 | → | N1:JTESTINP0_ECLKCASMUX_CORE_ECLKCASMUX4 |
| N1W1:JCIBMUXOUTC6 | → | N1:JTESTINP0_ECLKDIV_CORE_ECLKDIVB4_0 |
| N1W1:JCIBMUXOUTC6 | → | N1:JTESTINP0_ECLKDIV_CORE_ECLKDIVB4_1 |
| N1W1:JCIBMUXOUTC6 | → | N1:JTESTINP0_ECLKDIV_CORE_ECLKDIVB4_2 |
| N1W1:JCIBMUXOUTC6 | → | N1:JTESTINP0_ECLKDIV_CORE_ECLKDIVB4_3 |
| N1W1:JCIBMUXOUTA7 | → | N1:JTESTINP1_ECLKBANK_CORE_ECLKBANK4 |
| N1W1:JCIBMUXOUTB3 | → | N1:JTESTINP1_ECLKCASMUX_CORE_ECLKCASMUX4 |
| N1W1:JCIBMUXOUTC7 | → | N1:JTESTINP1_ECLKDIV_CORE_ECLKDIVB4_0 |
| N1W1:JCIBMUXOUTC7 | → | N1:JTESTINP1_ECLKDIV_CORE_ECLKDIVB4_1 |
| N1W1:JCIBMUXOUTC7 | → | N1:JTESTINP1_ECLKDIV_CORE_ECLKDIVB4_2 |
| N1W1:JCIBMUXOUTC7 | → | N1:JTESTINP1_ECLKDIV_CORE_ECLKDIVB4_3 |
| N1W1:JCIBMUXOUTB0 | → | N1:JTESTINP2_ECLKBANK_CORE_ECLKBANK4 |
| N1W1:JCIBMUXOUTD0 | → | N1:JTESTINP2_ECLKDIV_CORE_ECLKDIVB4_0 |
| N1W1:JCIBMUXOUTD0 | → | N1:JTESTINP2_ECLKDIV_CORE_ECLKDIVB4_1 |
| N1W1:JCIBMUXOUTD0 | → | N1:JTESTINP2_ECLKDIV_CORE_ECLKDIVB4_2 |
| N1W1:JCIBMUXOUTD0 | → | N1:JTESTINP2_ECLKDIV_CORE_ECLKDIVB4_3 |
| N1W1:JCIBMUXOUTB1 | → | N1:JTESTINP3_ECLKBANK_CORE_ECLKBANK4 |
| N1W1:JCIBMUXOUTD1 | → | N1:JTESTINP3_ECLKDIV_CORE_ECLKDIVB4_0 |
| N1W1:JCIBMUXOUTD1 | → | N1:JTESTINP3_ECLKDIV_CORE_ECLKDIVB4_1 |
| N1W1:JCIBMUXOUTD1 | → | N1:JTESTINP3_ECLKDIV_CORE_ECLKDIVB4_2 |
| N1W1:JCIBMUXOUTD1 | → | N1:JTESTINP3_ECLKDIV_CORE_ECLKDIVB4_3 |
| N1:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC4_0 | → | N1E1:JECLKCAS1M0_ECLKCASMUX_CORE_ECLKCASMUX3 |
| N1:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC4_1 | → | N1E1:JECLKCAS1M1_ECLKCASMUX_CORE_ECLKCASMUX3 |
| N1:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC4_2 | → | N1E1:JECLKCAS1M2_ECLKCASMUX_CORE_ECLKCASMUX3 |
| N1:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC4_3 | → | N1E1:JECLKCAS1M3_ECLKCASMUX_CORE_ECLKCASMUX3 |
| G:JECLKOUT0_ECLKCASMUX_CORE_ECLKCASMUX4 | → | N1E1:JECLKTREE1_ECLKDDRR_0 |
| G:JECLKOUT1_ECLKCASMUX_CORE_ECLKCASMUX4 | → | N1E1:JECLKTREE1_ECLKDDRR_1 |
| G:JECLKOUT2_ECLKCASMUX_CORE_ECLKCASMUX4 | → | N1E1:JECLKTREE1_ECLKDDRR_2 |
| G:JECLKOUT3_ECLKCASMUX_CORE_ECLKCASMUX4 | → | N1E1:JECLKTREE1_ECLKDDRR_3 |
| N1:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC4_0 | → | N1W1:JECLKCAS0M0_ECLKCASMUX_CORE_ECLKCASMUX5 |
| N1:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC4_1 | → | N1W1:JECLKCAS0M1_ECLKCASMUX_CORE_ECLKCASMUX5 |
| N1:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC4_2 | → | N1W1:JECLKCAS0M2_ECLKCASMUX_CORE_ECLKCASMUX5 |
| N1:JECLKOUT_ECLKSYNC_CORE_ECLKSYNC4_3 | → | N1W1:JECLKCAS0M3_ECLKCASMUX_CORE_ECLKCASMUX5 |
| G:JECLKOUT0_ECLKCASMUX_CORE_ECLKCASMUX4 | → | N1W1:JECLKTREE1_ECLKDDRL_0 |
| G:JECLKOUT1_ECLKCASMUX_CORE_ECLKCASMUX4 | → | N1W1:JECLKTREE1_ECLKDDRL_1 |
| G:JECLKOUT2_ECLKCASMUX_CORE_ECLKCASMUX4 | → | N1W1:JECLKTREE1_ECLKDDRL_2 |
| G:JECLKOUT3_ECLKCASMUX_CORE_ECLKCASMUX4 | → | N1W1:JECLKTREE1_ECLKDDRL_3 |