SYSIO_B4_0_DQS1/DIFFIO18 (DIFFIO18_CORE) Bel Documentation

Bel Pins

PinWire
B JIOPAD_DIFFIO18_CORE_IOAtop level pad signal
I JPADDO_DIFFIO18_CORE_IOAoutput buffer input from fabric/IOLOGIC
T JPADDT_DIFFIO18_CORE_IOAoutput buffer tristate (0=driven, 1=hi-z)
O JPADDI_DIFFIO18_CORE_IOAinput buffer output to fabric/IOLOGIC
DOLP JDOLP_DIFFIO18_CORE_IOADPHY LP mode output buffer input
HSRXEN JHSRXEN_DIFFIO18_CORE_IOADPHY high-speed receiver enable
HSTXEN JHSTXEN_DIFFIO18_CORE_IOADPHY high-speed transmitter enable
INLP JINLP_DIFFIO18_CORE_IOADPHY LP mode input buffer output
INADC JINADC_DIFFIO18_CORE_IOAanalog signal out to ADC