OXIDE_COMB bels are half the combinational part of a SLICE. They implement a LUT4 and some surrounding logic. They can be used as a LUT4; LUT4 with carry (½CCU2); LUT4 with MUX2 ("0" half bels only). Bels in SLICEA and SLICEB can also be used as a 16-bit distributed RAM.
| Pin | Wire | ||
|---|---|---|---|
| A | ← | JA0_SLICED | LUT A input |
| B | ← | JB0_SLICED | LUT B input |
| C | ← | JC0_SLICED | LUT C input |
| D | ← | JD0_SLICED | LUT D input |
| FCI | ← | JFCI_SLICED | CCU2 fast carry input |
| F | → | JF0_SLICED | LUT/sum output |
| FCO | → | JINT_CARRY_SLICED | CCU2 fast carry output |
| SEL | ← | JSEL_SLICED | MUX2 select input |
| F1 | ← | JF1_SLICED | input from second LUT to MUX2 |
| OFX | → | JOFX0_SLICED | MUX2 output |