OXIDE_COMB bels are half the combinational part of a SLICE. They implement a LUT4 and some surrounding logic. They can be used as a LUT4; LUT4 with carry (½CCU2); LUT4 with MUX2 ("0" half bels only). Bels in SLICEA and SLICEB can also be used as a 16-bit distributed RAM.
| Pin | Wire | ||
|---|---|---|---|
| A | ← | JA0_SLICEA | LUT A input |
| B | ← | JB0_SLICEA | LUT B input |
| C | ← | JC0_SLICEA | LUT C input |
| D | ← | JD0_SLICEA | LUT D input |
| FCI | ← | JFCI_SLICEA | CCU2 fast carry input |
| F | → | JF0_SLICEA | LUT/sum output |
| FCO | → | JINT_CARRY_SLICEA | CCU2 fast carry output |
| SEL | ← | JSEL_SLICEA | MUX2 select input |
| F1 | ← | JF1_SLICEA | input from second LUT to MUX2 |
| OFX | → | JOFX0_SLICEA | MUX2 output |
| WAD0 | ← | JWAD0_SLICEA | LUTRAM write address 0 (from RAMW) |
| WAD1 | ← | JWAD1_SLICEA | LUTRAM write address 1 (from RAMW) |
| WAD2 | ← | JWAD2_SLICEA | LUTRAM write address 2 (from RAMW) |
| WAD3 | ← | JWAD3_SLICEA | LUTRAM write address 3 (from RAMW) |
| WDI | ← | JWDI0_SLICEA | LUTRAM write data (from RAMW) |
| WCK | ← | JWCK_SLICEA | LUTRAM write clock (from RAMW) |
| WRE | ← | JWRE_SLICEA | LUTRAM write enable (from RAMW) |