DDR_OSC_R/DDRDLL_CORE (DDRDLL_CORE) Bel Documentation

Bel Pins

PinWire
CODE0→ W1:JCODE0_DDRDLL_CORE_I1
CODE1→ W1:JCODE1_DDRDLL_CORE_I1
CODE2→ W1:JCODE2_DDRDLL_CORE_I1
CODE3→ W1:JCODE3_DDRDLL_CORE_I1
CODE4→ W1:JCODE4_DDRDLL_CORE_I1
CODE5→ W1:JCODE5_DDRDLL_CORE_I1
CODE6→ W1:JCODE6_DDRDLL_CORE_I1
CODE7→ W1:JCODE7_DDRDLL_CORE_I1
CODE8→ W1:JCODE8_DDRDLL_CORE_I1
DCNTL0→ W1:JDCNTL0_DDRDLL_CORE_I1
DCNTL1→ W1:JDCNTL1_DDRDLL_CORE_I1
DCNTL2→ W1:JDCNTL2_DDRDLL_CORE_I1
DCNTL3→ W1:JDCNTL3_DDRDLL_CORE_I1
DCNTL4→ W1:JDCNTL4_DDRDLL_CORE_I1
DCNTL5→ W1:JDCNTL5_DDRDLL_CORE_I1
DCNTL6→ W1:JDCNTL6_DDRDLL_CORE_I1
DCNTL7→ W1:JDCNTL7_DDRDLL_CORE_I1
DCNTL8→ W1:JDCNTL8_DDRDLL_CORE_I1
DIVOSCIB→ W1:JDIVOSCIB_DDRDLL_CORE_I1
LOCK→ W1:JLOCK_DDRDLL_CORE_I1
CLKIN← W1:JCLKIN_DDRDLL_CORE_I1
FREEZE← W1:JFREEZE_DDRDLL_CORE_I1
RST← W1:JRST_DDRDLL_CORE_I1
UDDCNTL_N← W1:JUDDCNTL_N_DDRDLL_CORE_I1