BMID_0_ECLK_1 Tile Documentation

Tile Bels

NameType
DCC_B0 DCC
DCC_B1 DCC
DCC_B2 DCC
DCC_B3 DCC
DCC_B4 DCC
DCC_B5 DCC
DCC_B6 DCC
DCC_B7 DCC
DCC_B8 DCC
DCC_B9 DCC
DCC_B10 DCC
DCC_B11 DCC
DCC_B12 DCC
DCC_B13 DCC
DCC_B14 DCC
DCC_B15 DCC
DCC_B16 DCC
DCC_B17 DCC
ECLKSYNC4A ECLKSYNC_CORE
ECLKSYNC4B ECLKSYNC_CORE
ECLKSYNC4C ECLKSYNC_CORE
ECLKSYNC4D ECLKSYNC_CORE
ECLKDIV4A ECLKDIV_CORE
ECLKDIV4B ECLKDIV_CORE
ECLKDIV4C ECLKDIV_CORE
ECLKDIV4D ECLKDIV_CORE

Config Bitmap

 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
B
B
B
B
 
B
B
B
B
 
B
B
B
B
 
B
B
B
B
 
B
B
B
B
 
B
B
B
B
 
B
B
B
B
 
B
B
B
B
 
B
B
B
B
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

Routing Muxes

Mux driving G:JVPFN0_BMID_CORE_BMIDMUX

Source F20B0 F21B0 F22B0 F23B0
G:JECLKDIV6_BMID_CORE_BMIDMUX 0 1 0 0
G:JLRCLKOS4_BMID_CORE_BMIDMUX 0 1 0 1
G:JECLKDIV0_BMID_CORE_BMIDMUX 0 1 1 0
G:JLRCLKOS2_BMID_CORE_BMIDMUX 0 1 1 1
G:JPCLKCIBB0_BMID_CORE_BMIDMUX 1 0 0 1
G:JECLKDIV10_BMID_CORE_BMIDMUX 1 0 1 1
G:JLLCLKOP_BMID_CORE_BMIDMUX 1 1 0 0
G:JPCLKT33_BMID_CORE_BMIDMUX 1 1 0 1
G:JPCLKT50_BMID_CORE_BMIDMUX 1 1 1 0
G:JPCLKT30_BMID_CORE_BMIDMUX 1 1 1 1

Mux driving G:JVPFN1_BMID_CORE_BMIDMUX

Source F25B0 F26B0 F27B0 F28B0
G:JPCLKCIBB1_BMID_CORE_BMIDMUX 0 1 0 0
G:JECLKDIV3_BMID_CORE_BMIDMUX 0 1 0 1
G:JECLKDIV8_BMID_CORE_BMIDMUX 0 1 1 0
G:JLRCLKOS5_BMID_CORE_BMIDMUX 0 1 1 1
G:JPCLKCIBB4_BMID_CORE_BMIDMUX 1 0 0 1
G:JPCLKCIBB2_BMID_CORE_BMIDMUX 1 0 1 1
G:JLLCLKOS4_BMID_CORE_BMIDMUX 1 1 0 0
G:JPCLKT42_BMID_CORE_BMIDMUX 1 1 0 1
G:JPCLKT51_BMID_CORE_BMIDMUX 1 1 1 0
G:JPCLKT31_BMID_CORE_BMIDMUX 1 1 1 1

Mux driving G:JVPFN2_BMID_CORE_BMIDMUX

Source F30B0 F31B0 F32B0 F33B0
G:JECLKDIV9_BMID_CORE_BMIDMUX 0 1 0 0
G:JLRCLKOS3_BMID_CORE_BMIDMUX 0 1 0 1
G:JECLKDIV1_BMID_CORE_BMIDMUX 0 1 1 0
G:JLRCLKOP_BMID_CORE_BMIDMUX 0 1 1 1
G:JPCLKCIBB5_BMID_CORE_BMIDMUX 1 0 0 1
G:JPCLKCIBB1_BMID_CORE_BMIDMUX 1 0 1 1
G:JLLCLKOS3_BMID_CORE_BMIDMUX 1 1 0 0
G:JPCLKT41_BMID_CORE_BMIDMUX 1 1 0 1
G:JPCLKT53_BMID_CORE_BMIDMUX 1 1 1 0
G:JPCLKT32_BMID_CORE_BMIDMUX 1 1 1 1

Mux driving G:JVPFN3_BMID_CORE_BMIDMUX

Source F35B0 F36B0 F37B0 F38B0
G:JECLKDIV11_BMID_CORE_BMIDMUX 0 1 0 0
G:JECLKDIV2_BMID_CORE_BMIDMUX 0 1 0 1
G:JECLKDIV6_BMID_CORE_BMIDMUX 0 1 1 0
G:JLLCLKOS5_BMID_CORE_BMIDMUX 0 1 1 1
G:JPCLKCIBB3_BMID_CORE_BMIDMUX 1 0 1 1
G:JLLCLKOS2_BMID_CORE_BMIDMUX 1 1 0 0
G:JPCLKT33_BMID_CORE_BMIDMUX 1 1 0 1
G:JPCLKT52_BMID_CORE_BMIDMUX 1 1 1 0
G:JPCLKT30_BMID_CORE_BMIDMUX 1 1 1 1

Mux driving G:JVPFN4_BMID_CORE_BMIDMUX

Source F40B0 F41B0 F42B0 F43B0
G:JECLKDIV10_BMID_CORE_BMIDMUX 0 1 0 0
G:JECLKDIV0_BMID_CORE_BMIDMUX 0 1 0 1
G:JECLKDIV3_BMID_CORE_BMIDMUX 0 1 1 0
G:JLRCLKOS_BMID_CORE_BMIDMUX 0 1 1 1
G:JPCLKCIBB2_BMID_CORE_BMIDMUX 1 0 0 1
G:JPCLKCIBB0_BMID_CORE_BMIDMUX 1 0 1 1
G:JLLCLKOP_BMID_CORE_BMIDMUX 1 1 0 0
G:JPCLKT43_BMID_CORE_BMIDMUX 1 1 0 1
G:JPCLKT52_BMID_CORE_BMIDMUX 1 1 1 0
G:JPCLKT40_BMID_CORE_BMIDMUX 1 1 1 1

Mux driving G:JVPFN5_BMID_CORE_BMIDMUX

Source F45B0 F46B0 F47B0 F48B0
G:JPCLKCIBB2_BMID_CORE_BMIDMUX 0 1 0 0
G:JECLKDIV7_BMID_CORE_BMIDMUX 0 1 0 1
G:JECLKDIV10_BMID_CORE_BMIDMUX 0 1 1 0
G:JECLKDIV4_BMID_CORE_BMIDMUX 0 1 1 1
G:JPCLKCIBB4_BMID_CORE_BMIDMUX 1 0 1 1
G:JLRCLKOP_BMID_CORE_BMIDMUX 1 1 0 0
G:JPCLKT41_BMID_CORE_BMIDMUX 1 1 0 1
G:JLLCLKOS_BMID_CORE_BMIDMUX 1 1 1 0
G:JPCLKT32_BMID_CORE_BMIDMUX 1 1 1 1

Mux driving G:JVPFN6_BMID_CORE_BMIDMUX

Source F50B0 F51B0 F52B0 F53B0
G:JPCLKCIBB1_BMID_CORE_BMIDMUX 0 1 0 0
G:JECLKDIV5_BMID_CORE_BMIDMUX 0 1 0 1
G:JECLKDIV7_BMID_CORE_BMIDMUX 0 1 1 0
G:JLRCLKOS_BMID_CORE_BMIDMUX 0 1 1 1
G:JPCLKCIBB5_BMID_CORE_BMIDMUX 1 0 1 1
G:JLLCLKOS_BMID_CORE_BMIDMUX 1 1 0 0
G:JPCLKT42_BMID_CORE_BMIDMUX 1 1 0 1
G:JPCLKT51_BMID_CORE_BMIDMUX 1 1 1 0
G:JPCLKT31_BMID_CORE_BMIDMUX 1 1 1 1

Mux driving G:JVPFN7_BMID_CORE_BMIDMUX

Source F55B0 F56B0 F57B0 F58B0
G:JECLKDIV5_BMID_CORE_BMIDMUX 0 1 0 0
G:JLRCLKOS4_BMID_CORE_BMIDMUX 0 1 0 1
G:JECLKDIV1_BMID_CORE_BMIDMUX 0 1 1 0
G:JLRCLKOS2_BMID_CORE_BMIDMUX 0 1 1 1
G:JPCLKCIBB0_BMID_CORE_BMIDMUX 1 0 0 1
G:JECLKDIV9_BMID_CORE_BMIDMUX 1 0 1 1
G:JLLCLKOS3_BMID_CORE_BMIDMUX 1 1 0 0
G:JPCLKT43_BMID_CORE_BMIDMUX 1 1 0 1
G:JLLCLKOP_BMID_CORE_BMIDMUX 1 1 1 0
G:JPCLKT40_BMID_CORE_BMIDMUX 1 1 1 1

Mux driving G:JVPFN8_BMID_CORE_BMIDMUX

Source F60B0 F61B0 F62B0 F63B0
G:JECLKDIV6_BMID_CORE_BMIDMUX 0 1 0 0
G:JLRCLKOS5_BMID_CORE_BMIDMUX 0 1 0 1
G:JECLKDIV2_BMID_CORE_BMIDMUX 0 1 1 0
G:JLRCLKOS3_BMID_CORE_BMIDMUX 0 1 1 1
G:JPCLKCIBB3_BMID_CORE_BMIDMUX 1 0 0 1
G:JECLKDIV11_BMID_CORE_BMIDMUX 1 0 1 1
G:JLLCLKOS5_BMID_CORE_BMIDMUX 1 1 0 0
G:JPCLKT50_BMID_CORE_BMIDMUX 1 1 0 1
G:JLLCLKOS2_BMID_CORE_BMIDMUX 1 1 1 0
G:JPCLKT33_BMID_CORE_BMIDMUX 1 1 1 1

Fixed Connections

SourceSink
N1W2:JCIBMUXOUTD7→ G:JPCLKCIBB0_BMID_CORE_BMIDMUX
N1W1:JCIBMUXOUTD7→ G:JPCLKCIBB1_BMID_CORE_BMIDMUX
N1:JCIBMUXOUTD7→ G:JPCLKCIBB2_BMID_CORE_BMIDMUX
N1E1:JCIBMUXOUTD7→ G:JPCLKCIBB3_BMID_CORE_BMIDMUX
N1E2:JCIBMUXOUTD7→ G:JPCLKCIBB4_BMID_CORE_BMIDMUX
N1E3:JCIBMUXOUTD7→ G:JPCLKCIBB5_BMID_CORE_BMIDMUX
N1W3:JCLKOUT_DLLDEL_CORE_I0→ G:JPCLKT0_ECLKBANK_CORE_ECLKBANK4
W15:JINCK_IOLOGIC_CORE_I_GEARING_PIC_TOP_A→ G:JPCLKT1_ECLKBANK_CORE_ECLKBANK4
W15:JPADDI_DIFFIO18A_CORE_IOA→ G:JPCLKT1_ECLKBANK_CORE_ECLKBANK4
N1E4:JCLKOUT_DLLDEL_CORE_I0→ G:JPCLKT2_ECLKBANK_CORE_ECLKBANK4
N1E5:JCLKOUT_DLLDEL_CORE_I0→ G:JPCLKT30_BMID_CORE_BMIDMUX
E45:JINCK_IOLOGIC_CORE_I_GEARING_PIC_TOP_A→ G:JPCLKT31_BMID_CORE_BMIDMUX
E45:JPADDI_DIFFIO18A_CORE_IOA→ G:JPCLKT31_BMID_CORE_BMIDMUX
N1E6:JCLKOUT_DLLDEL_CORE_I0→ G:JPCLKT32_BMID_CORE_BMIDMUX
E81:JINCK_IOLOGIC_CORE_I_GEARING_PIC_TOP_A→ G:JPCLKT33_BMID_CORE_BMIDMUX
E81:JPADDI_DIFFIO18A_CORE_IOA→ G:JPCLKT33_BMID_CORE_BMIDMUX
E33:JINCK_IOLOGIC_CORE_I_GEARING_PIC_TOP_A→ G:JPCLKT3_ECLKBANK_CORE_ECLKBANK4
E33:JPADDI_DIFFIO18A_CORE_IOA→ G:JPCLKT3_ECLKBANK_CORE_ECLKBANK4
N1W3:JCLKOUT_DLLDEL_CORE_I0→ G:JPCLKT40_BMID_CORE_BMIDMUX
W15:JINCK_IOLOGIC_CORE_I_GEARING_PIC_TOP_A→ G:JPCLKT41_BMID_CORE_BMIDMUX
W15:JPADDI_DIFFIO18A_CORE_IOA→ G:JPCLKT41_BMID_CORE_BMIDMUX
N1E4:JCLKOUT_DLLDEL_CORE_I0→ G:JPCLKT42_BMID_CORE_BMIDMUX
E33:JINCK_IOLOGIC_CORE_I_GEARING_PIC_TOP_A→ G:JPCLKT43_BMID_CORE_BMIDMUX
E33:JPADDI_DIFFIO18A_CORE_IOA→ G:JPCLKT43_BMID_CORE_BMIDMUX
N1W5:JCLKOUT_DLLDEL_CORE_I0→ G:JPCLKT50_BMID_CORE_BMIDMUX
W63:JINCK_IOLOGIC_CORE_I_GEARING_PIC_TOP_A→ G:JPCLKT51_BMID_CORE_BMIDMUX
W63:JPADDI_DIFFIO18A_CORE_IOA→ G:JPCLKT51_BMID_CORE_BMIDMUX
N1W4:JCLKOUT_DLLDEL_CORE_I0→ G:JPCLKT52_BMID_CORE_BMIDMUX
W27:JINCK_IOLOGIC_CORE_I_GEARING_PIC_TOP_A→ G:JPCLKT53_BMID_CORE_BMIDMUX
W27:JPADDI_DIFFIO18A_CORE_IOA→ G:JPCLKT53_BMID_CORE_BMIDMUX
N1:JCIBMUXOUTA0→ G:JTESTINP0_BMID_CORE_BMIDMUX
N1:JCIBMUXOUTA1→ G:JTESTINP1_BMID_CORE_BMIDMUX
N1:JCIBMUXOUTA2→ G:JTESTINP2_BMID_CORE_BMIDMUX
N1:JCIBMUXOUTA3→ G:JTESTINP3_BMID_CORE_BMIDMUX
N1:JCLKO_DCC_DCC0→ G:JVPFN0_CMUX_CORE_CMUX0
N1:JCLKO_DCC_DCC0→ G:JVPFN0_CMUX_CORE_CMUX1
N1:JCLKO_DCC_DCC0→ G:JVPFN0_CMUX_CORE_CMUX2
N1:JCLKO_DCC_DCC0→ G:JVPFN0_CMUX_CORE_CMUX3
N1:JCLKO_DCC_DCC0→ G:JVPFN0_DCSMUX_CORE_DCSMUX0
N1:JCLKO_DCC_DCC0→ G:JVPFN0_DCSMUX_CORE_DCSMUX1
N1:JCLKO_DCC_DCC0→ G:JVPFN0_DCSMUX_CORE_DCSMUX2
N1:JCLKO_DCC_DCC0→ G:JVPFN0_DCSMUX_CORE_DCSMUX3
N1:JCLKO_DCC_DCC10→ G:JVPFN10_CMUX_CORE_CMUX0
N1:JCLKO_DCC_DCC10→ G:JVPFN10_CMUX_CORE_CMUX1
N1:JCLKO_DCC_DCC10→ G:JVPFN10_CMUX_CORE_CMUX2
N1:JCLKO_DCC_DCC10→ G:JVPFN10_CMUX_CORE_CMUX3
N1:JCLKO_DCC_DCC10→ G:JVPFN10_DCSMUX_CORE_DCSMUX0
N1:JCLKO_DCC_DCC10→ G:JVPFN10_DCSMUX_CORE_DCSMUX1
N1:JCLKO_DCC_DCC10→ G:JVPFN10_DCSMUX_CORE_DCSMUX2
N1:JCLKO_DCC_DCC10→ G:JVPFN10_DCSMUX_CORE_DCSMUX3
N1:JCLKO_DCC_DCC11→ G:JVPFN11_CMUX_CORE_CMUX0
N1:JCLKO_DCC_DCC11→ G:JVPFN11_CMUX_CORE_CMUX1
N1:JCLKO_DCC_DCC11→ G:JVPFN11_CMUX_CORE_CMUX2
N1:JCLKO_DCC_DCC11→ G:JVPFN11_CMUX_CORE_CMUX3
N1:JCLKO_DCC_DCC11→ G:JVPFN11_DCSMUX_CORE_DCSMUX0
N1:JCLKO_DCC_DCC11→ G:JVPFN11_DCSMUX_CORE_DCSMUX1
N1:JCLKO_DCC_DCC11→ G:JVPFN11_DCSMUX_CORE_DCSMUX2
N1:JCLKO_DCC_DCC11→ G:JVPFN11_DCSMUX_CORE_DCSMUX3
N1:JCLKO_DCC_DCC12→ G:JVPFN12_CMUX_CORE_CMUX0
N1:JCLKO_DCC_DCC12→ G:JVPFN12_CMUX_CORE_CMUX1
N1:JCLKO_DCC_DCC12→ G:JVPFN12_CMUX_CORE_CMUX2
N1:JCLKO_DCC_DCC12→ G:JVPFN12_CMUX_CORE_CMUX3
N1:JCLKO_DCC_DCC12→ G:JVPFN12_DCSMUX_CORE_DCSMUX0
N1:JCLKO_DCC_DCC12→ G:JVPFN12_DCSMUX_CORE_DCSMUX1
N1:JCLKO_DCC_DCC12→ G:JVPFN12_DCSMUX_CORE_DCSMUX2
N1:JCLKO_DCC_DCC12→ G:JVPFN12_DCSMUX_CORE_DCSMUX3
N1:JCLKO_DCC_DCC13→ G:JVPFN13_CMUX_CORE_CMUX0
N1:JCLKO_DCC_DCC13→ G:JVPFN13_CMUX_CORE_CMUX1
N1:JCLKO_DCC_DCC13→ G:JVPFN13_CMUX_CORE_CMUX2
N1:JCLKO_DCC_DCC13→ G:JVPFN13_CMUX_CORE_CMUX3
N1:JCLKO_DCC_DCC13→ G:JVPFN13_DCSMUX_CORE_DCSMUX0
N1:JCLKO_DCC_DCC13→ G:JVPFN13_DCSMUX_CORE_DCSMUX1
N1:JCLKO_DCC_DCC13→ G:JVPFN13_DCSMUX_CORE_DCSMUX2
N1:JCLKO_DCC_DCC13→ G:JVPFN13_DCSMUX_CORE_DCSMUX3
N1:JCLKO_DCC_DCC14→ G:JVPFN14_CMUX_CORE_CMUX0
N1:JCLKO_DCC_DCC14→ G:JVPFN14_CMUX_CORE_CMUX1
N1:JCLKO_DCC_DCC14→ G:JVPFN14_CMUX_CORE_CMUX2
N1:JCLKO_DCC_DCC14→ G:JVPFN14_CMUX_CORE_CMUX3
N1:JCLKO_DCC_DCC14→ G:JVPFN14_DCSMUX_CORE_DCSMUX0
N1:JCLKO_DCC_DCC14→ G:JVPFN14_DCSMUX_CORE_DCSMUX1
N1:JCLKO_DCC_DCC14→ G:JVPFN14_DCSMUX_CORE_DCSMUX2
N1:JCLKO_DCC_DCC14→ G:JVPFN14_DCSMUX_CORE_DCSMUX3
N1:JCLKO_DCC_DCC15→ G:JVPFN15_CMUX_CORE_CMUX0
N1:JCLKO_DCC_DCC15→ G:JVPFN15_CMUX_CORE_CMUX1
N1:JCLKO_DCC_DCC15→ G:JVPFN15_CMUX_CORE_CMUX2
N1:JCLKO_DCC_DCC15→ G:JVPFN15_CMUX_CORE_CMUX3
N1:JCLKO_DCC_DCC15→ G:JVPFN15_DCSMUX_CORE_DCSMUX0
N1:JCLKO_DCC_DCC15→ G:JVPFN15_DCSMUX_CORE_DCSMUX1
N1:JCLKO_DCC_DCC15→ G:JVPFN15_DCSMUX_CORE_DCSMUX2
N1:JCLKO_DCC_DCC15→ G:JVPFN15_DCSMUX_CORE_DCSMUX3
N1:JCLKO_DCC_DCC16→ G:JVPFN16_CMUX_CORE_CMUX0
N1:JCLKO_DCC_DCC16→ G:JVPFN16_CMUX_CORE_CMUX1
N1:JCLKO_DCC_DCC16→ G:JVPFN16_CMUX_CORE_CMUX2
N1:JCLKO_DCC_DCC16→ G:JVPFN16_CMUX_CORE_CMUX3
N1:JCLKO_DCC_DCC16→ G:JVPFN16_DCSMUX_CORE_DCSMUX0
N1:JCLKO_DCC_DCC16→ G:JVPFN16_DCSMUX_CORE_DCSMUX1
N1:JCLKO_DCC_DCC16→ G:JVPFN16_DCSMUX_CORE_DCSMUX2
N1:JCLKO_DCC_DCC16→ G:JVPFN16_DCSMUX_CORE_DCSMUX3
N1:JCLKO_DCC_DCC17→ G:JVPFN17_CMUX_CORE_CMUX0
N1:JCLKO_DCC_DCC17→ G:JVPFN17_CMUX_CORE_CMUX1
N1:JCLKO_DCC_DCC17→ G:JVPFN17_CMUX_CORE_CMUX2
N1:JCLKO_DCC_DCC17→ G:JVPFN17_CMUX_CORE_CMUX3
N1:JCLKO_DCC_DCC17→ G:JVPFN17_DCSMUX_CORE_DCSMUX0
N1:JCLKO_DCC_DCC17→ G:JVPFN17_DCSMUX_CORE_DCSMUX1
N1:JCLKO_DCC_DCC17→ G:JVPFN17_DCSMUX_CORE_DCSMUX2
N1:JCLKO_DCC_DCC17→ G:JVPFN17_DCSMUX_CORE_DCSMUX3
N1:JCLKO_DCC_DCC1→ G:JVPFN1_CMUX_CORE_CMUX0
N1:JCLKO_DCC_DCC1→ G:JVPFN1_CMUX_CORE_CMUX1
N1:JCLKO_DCC_DCC1→ G:JVPFN1_CMUX_CORE_CMUX2
N1:JCLKO_DCC_DCC1→ G:JVPFN1_CMUX_CORE_CMUX3
N1:JCLKO_DCC_DCC1→ G:JVPFN1_DCSMUX_CORE_DCSMUX0
N1:JCLKO_DCC_DCC1→ G:JVPFN1_DCSMUX_CORE_DCSMUX1
N1:JCLKO_DCC_DCC1→ G:JVPFN1_DCSMUX_CORE_DCSMUX2
N1:JCLKO_DCC_DCC1→ G:JVPFN1_DCSMUX_CORE_DCSMUX3
N1:JCLKO_DCC_DCC2→ G:JVPFN2_CMUX_CORE_CMUX0
N1:JCLKO_DCC_DCC2→ G:JVPFN2_CMUX_CORE_CMUX1
N1:JCLKO_DCC_DCC2→ G:JVPFN2_CMUX_CORE_CMUX2
N1:JCLKO_DCC_DCC2→ G:JVPFN2_CMUX_CORE_CMUX3
N1:JCLKO_DCC_DCC2→ G:JVPFN2_DCSMUX_CORE_DCSMUX0
N1:JCLKO_DCC_DCC2→ G:JVPFN2_DCSMUX_CORE_DCSMUX1
N1:JCLKO_DCC_DCC2→ G:JVPFN2_DCSMUX_CORE_DCSMUX2
N1:JCLKO_DCC_DCC2→ G:JVPFN2_DCSMUX_CORE_DCSMUX3
N1:JCLKO_DCC_DCC3→ G:JVPFN3_CMUX_CORE_CMUX0
N1:JCLKO_DCC_DCC3→ G:JVPFN3_CMUX_CORE_CMUX1
N1:JCLKO_DCC_DCC3→ G:JVPFN3_CMUX_CORE_CMUX2
N1:JCLKO_DCC_DCC3→ G:JVPFN3_CMUX_CORE_CMUX3
N1:JCLKO_DCC_DCC3→ G:JVPFN3_DCSMUX_CORE_DCSMUX0
N1:JCLKO_DCC_DCC3→ G:JVPFN3_DCSMUX_CORE_DCSMUX1
N1:JCLKO_DCC_DCC3→ G:JVPFN3_DCSMUX_CORE_DCSMUX2
N1:JCLKO_DCC_DCC3→ G:JVPFN3_DCSMUX_CORE_DCSMUX3
N1:JCLKO_DCC_DCC4→ G:JVPFN4_CMUX_CORE_CMUX0
N1:JCLKO_DCC_DCC4→ G:JVPFN4_CMUX_CORE_CMUX1
N1:JCLKO_DCC_DCC4→ G:JVPFN4_CMUX_CORE_CMUX2
N1:JCLKO_DCC_DCC4→ G:JVPFN4_CMUX_CORE_CMUX3
N1:JCLKO_DCC_DCC4→ G:JVPFN4_DCSMUX_CORE_DCSMUX0
N1:JCLKO_DCC_DCC4→ G:JVPFN4_DCSMUX_CORE_DCSMUX1
N1:JCLKO_DCC_DCC4→ G:JVPFN4_DCSMUX_CORE_DCSMUX2
N1:JCLKO_DCC_DCC4→ G:JVPFN4_DCSMUX_CORE_DCSMUX3
N1:JCLKO_DCC_DCC5→ G:JVPFN5_CMUX_CORE_CMUX0
N1:JCLKO_DCC_DCC5→ G:JVPFN5_CMUX_CORE_CMUX1
N1:JCLKO_DCC_DCC5→ G:JVPFN5_CMUX_CORE_CMUX2
N1:JCLKO_DCC_DCC5→ G:JVPFN5_CMUX_CORE_CMUX3
N1:JCLKO_DCC_DCC5→ G:JVPFN5_DCSMUX_CORE_DCSMUX0
N1:JCLKO_DCC_DCC5→ G:JVPFN5_DCSMUX_CORE_DCSMUX1
N1:JCLKO_DCC_DCC5→ G:JVPFN5_DCSMUX_CORE_DCSMUX2
N1:JCLKO_DCC_DCC5→ G:JVPFN5_DCSMUX_CORE_DCSMUX3
N1:JCLKO_DCC_DCC6→ G:JVPFN6_CMUX_CORE_CMUX0
N1:JCLKO_DCC_DCC6→ G:JVPFN6_CMUX_CORE_CMUX1
N1:JCLKO_DCC_DCC6→ G:JVPFN6_CMUX_CORE_CMUX2
N1:JCLKO_DCC_DCC6→ G:JVPFN6_CMUX_CORE_CMUX3
N1:JCLKO_DCC_DCC6→ G:JVPFN6_DCSMUX_CORE_DCSMUX0
N1:JCLKO_DCC_DCC6→ G:JVPFN6_DCSMUX_CORE_DCSMUX1
N1:JCLKO_DCC_DCC6→ G:JVPFN6_DCSMUX_CORE_DCSMUX2
N1:JCLKO_DCC_DCC6→ G:JVPFN6_DCSMUX_CORE_DCSMUX3
N1:JCLKO_DCC_DCC7→ G:JVPFN7_CMUX_CORE_CMUX0
N1:JCLKO_DCC_DCC7→ G:JVPFN7_CMUX_CORE_CMUX1
N1:JCLKO_DCC_DCC7→ G:JVPFN7_CMUX_CORE_CMUX2
N1:JCLKO_DCC_DCC7→ G:JVPFN7_CMUX_CORE_CMUX3
N1:JCLKO_DCC_DCC7→ G:JVPFN7_DCSMUX_CORE_DCSMUX0
N1:JCLKO_DCC_DCC7→ G:JVPFN7_DCSMUX_CORE_DCSMUX1
N1:JCLKO_DCC_DCC7→ G:JVPFN7_DCSMUX_CORE_DCSMUX2
N1:JCLKO_DCC_DCC7→ G:JVPFN7_DCSMUX_CORE_DCSMUX3
N1:JCLKO_DCC_DCC8→ G:JVPFN8_CMUX_CORE_CMUX0
N1:JCLKO_DCC_DCC8→ G:JVPFN8_CMUX_CORE_CMUX1
N1:JCLKO_DCC_DCC8→ G:JVPFN8_CMUX_CORE_CMUX2
N1:JCLKO_DCC_DCC8→ G:JVPFN8_CMUX_CORE_CMUX3
N1:JCLKO_DCC_DCC8→ G:JVPFN8_DCSMUX_CORE_DCSMUX0
N1:JCLKO_DCC_DCC8→ G:JVPFN8_DCSMUX_CORE_DCSMUX1
N1:JCLKO_DCC_DCC8→ G:JVPFN8_DCSMUX_CORE_DCSMUX2
N1:JCLKO_DCC_DCC8→ G:JVPFN8_DCSMUX_CORE_DCSMUX3
N1:JCLKO_DCC_DCC9→ G:JVPFN9_CMUX_CORE_CMUX0
N1:JCLKO_DCC_DCC9→ G:JVPFN9_CMUX_CORE_CMUX1
N1:JCLKO_DCC_DCC9→ G:JVPFN9_CMUX_CORE_CMUX2
N1:JCLKO_DCC_DCC9→ G:JVPFN9_CMUX_CORE_CMUX3
N1:JCLKO_DCC_DCC9→ G:JVPFN9_DCSMUX_CORE_DCSMUX0
N1:JCLKO_DCC_DCC9→ G:JVPFN9_DCSMUX_CORE_DCSMUX1
N1:JCLKO_DCC_DCC9→ G:JVPFN9_DCSMUX_CORE_DCSMUX2
N1:JCLKO_DCC_DCC9→ G:JVPFN9_DCSMUX_CORE_DCSMUX3
N1:JCIBMUXOUTC0→ N1:JCE_DCC_DCC0
N1:JCIBMUXOUTC1→ N1:JCE_DCC_DCC1
N1E1:JCIBMUXOUTA6→ N1:JCE_DCC_DCC10
N1E1:JCIBMUXOUTA7→ N1:JCE_DCC_DCC11
N1E1:JCIBMUXOUTC0→ N1:JCE_DCC_DCC12
N1E1:JCIBMUXOUTC1→ N1:JCE_DCC_DCC13
N1E1:JCIBMUXOUTC2→ N1:JCE_DCC_DCC14
N1E1:JCIBMUXOUTC3→ N1:JCE_DCC_DCC15
N1E1:JCIBMUXOUTC4→ N1:JCE_DCC_DCC16
N1E1:JCIBMUXOUTC5→ N1:JCE_DCC_DCC17
N1:JCIBMUXOUTC2→ N1:JCE_DCC_DCC2
N1:JCIBMUXOUTC3→ N1:JCE_DCC_DCC3
N1:JCIBMUXOUTC4→ N1:JCE_DCC_DCC4
N1:JCIBMUXOUTC5→ N1:JCE_DCC_DCC5
N1:JCIBMUXOUTC6→ N1:JCE_DCC_DCC6
N1:JCIBMUXOUTC7→ N1:JCE_DCC_DCC7
N1E1:JCIBMUXOUTA4→ N1:JCE_DCC_DCC8
N1E1:JCIBMUXOUTA5→ N1:JCE_DCC_DCC9
G:JVPFN0_BMID_CORE_BMIDMUX→ N1:JCLKI_DCC_DCC0
G:JVPFN1_BMID_CORE_BMIDMUX→ N1:JCLKI_DCC_DCC1
G:JVPFN10_BMID_CORE_BMIDMUX→ N1:JCLKI_DCC_DCC10
G:JVPFN11_BMID_CORE_BMIDMUX→ N1:JCLKI_DCC_DCC11
G:JVPFN12_BMID_CORE_BMIDMUX→ N1:JCLKI_DCC_DCC12
G:JVPFN13_BMID_CORE_BMIDMUX→ N1:JCLKI_DCC_DCC13
G:JVPFN14_BMID_CORE_BMIDMUX→ N1:JCLKI_DCC_DCC14
G:JVPFN15_BMID_CORE_BMIDMUX→ N1:JCLKI_DCC_DCC15
G:JVPFN16_BMID_CORE_BMIDMUX→ N1:JCLKI_DCC_DCC16
G:JVPFN17_BMID_CORE_BMIDMUX→ N1:JCLKI_DCC_DCC17
G:JVPFN2_BMID_CORE_BMIDMUX→ N1:JCLKI_DCC_DCC2
G:JVPFN3_BMID_CORE_BMIDMUX→ N1:JCLKI_DCC_DCC3
G:JVPFN4_BMID_CORE_BMIDMUX→ N1:JCLKI_DCC_DCC4
G:JVPFN5_BMID_CORE_BMIDMUX→ N1:JCLKI_DCC_DCC5
G:JVPFN6_BMID_CORE_BMIDMUX→ N1:JCLKI_DCC_DCC6
G:JVPFN7_BMID_CORE_BMIDMUX→ N1:JCLKI_DCC_DCC7
G:JVPFN8_BMID_CORE_BMIDMUX→ N1:JCLKI_DCC_DCC8
G:JVPFN9_BMID_CORE_BMIDMUX→ N1:JCLKI_DCC_DCC9
N1:JCLKI_DCC_DCC0→ N1:JCLKO_DCC_DCC0
N1:JCLKI_DCC_DCC1→ N1:JCLKO_DCC_DCC1
N1:JCLKI_DCC_DCC10→ N1:JCLKO_DCC_DCC10
N1:JCLKI_DCC_DCC11→ N1:JCLKO_DCC_DCC11
N1:JCLKI_DCC_DCC12→ N1:JCLKO_DCC_DCC12
N1:JCLKI_DCC_DCC13→ N1:JCLKO_DCC_DCC13
N1:JCLKI_DCC_DCC14→ N1:JCLKO_DCC_DCC14
N1:JCLKI_DCC_DCC15→ N1:JCLKO_DCC_DCC15
N1:JCLKI_DCC_DCC16→ N1:JCLKO_DCC_DCC16
N1:JCLKI_DCC_DCC17→ N1:JCLKO_DCC_DCC17
N1:JCLKI_DCC_DCC2→ N1:JCLKO_DCC_DCC2
N1:JCLKI_DCC_DCC3→ N1:JCLKO_DCC_DCC3
N1:JCLKI_DCC_DCC4→ N1:JCLKO_DCC_DCC4
N1:JCLKI_DCC_DCC5→ N1:JCLKO_DCC_DCC5
N1:JCLKI_DCC_DCC6→ N1:JCLKO_DCC_DCC6
N1:JCLKI_DCC_DCC7→ N1:JCLKO_DCC_DCC7
N1:JCLKI_DCC_DCC8→ N1:JCLKO_DCC_DCC8
N1:JCLKI_DCC_DCC9→ N1:JCLKO_DCC_DCC9