SYSIO_B5_0/PIOB (SEIO18_CORE) Bel Documentation

Bel Pins

PinWire
B↔ JIOPAD_SEIO18_CORE_IOBtop level pad signal
I← JPADDO_SEIO18_CORE_IOBoutput buffer input from fabric/IOLOGIC
T← JPADDT_SEIO18_CORE_IOBoutput buffer tristate (0=driven, 1=hi-z)
O→ JPADDI_SEIO18_CORE_IOBinput buffer output to fabric/IOLOGIC
DOLP← JDOLP_SEIO18_CORE_IOBDPHY LP mode output buffer input
INLP→ JINLP_SEIO18_CORE_IOBDPHY LP mode input buffer output
INADC→ JINADC_SEIO18_CORE_IOBanalog signal out to ADC