SEIO33_CORE bels implement the buffer side of the wide range (3.3V capable) IOs. Note that the logical parts of these pins (registers, delay and DDR) are implemented using the SIOLOGIC bel. These pins can be used as single ended input/inout/output; or two outputs can be used in "pseudo differential" mode - differential input is not possible.
| Pin | Wire | ||
|---|---|---|---|
| B | ↔ | JPAD_SEIO33_CORE_IOA | top level pad signal |
| I | ← | JPADDO_SEIO33_CORE_IOA | output buffer input from fabric/IOLOGIC |
| T | ← | JPADDT_SEIO33_CORE_IOA | output buffer tristate (0=driven, 1=hi-z) |
| O | → | JPADDI_SEIO33_CORE_IOA | input buffer output to fabric/IOLOGIC |
| I3CRESEN | ← | JI3CRESEN_SEIO33_CORE_IOA | I3C strong pullup enable |
| I3CWKPU | ← | JI3CWKPU_SEIO33_CORE_IOA | I3C weak pullup enable |